Vertical Compute expands partnership with imec to accelerate commercial manufacturing of Vertically Integrated Memory (VIM)

Leuven, Belgium, 11 November 2026 – Joint engineering effort integrates Vertical Compute’s memory-on-logic architecture with imec’s EU-funded NanoIC pilot line, moving breakthrough chiplet technology from validation to 16nm production.

AI is scaling faster than the infrastructure that supports it. As models grow and workloads become more data-intensive, moving data between memory and compute has become the dominant bottleneck, driving up cost, energy consumption, and system complexity across the entire stack.

This is no longer just a performance issue. It is a structural constraint shaping where AI can run, who can afford it, and how far it can scale.

Today, Vertical Compute announces an expanded partnership with imec to accelerate the commercial deployment of its vertically integrated memory (VIM) technology. Moving beyond an initial R&D service agreement, the two organizations will now operate in a deeply integrated engineering model to bring this architectural shift to market.

From validation to scalable production
The collaboration focuses on the complete validation of Vertical Compute’s test chip in 40nm and prepares the manufacturing of its first pre-production product in 16nm. By combining standard commercial foundry processes with advanced VIM integration at imec, the partnership removes the traditional barriers to scaling next-generation memory architectures.

Moving beyond the limits of external memory
Vertical Compute’s technology fundamentally changes how data flows inside a chip by stacking high-density magnetic memory directly above compute logic, reducing the path between data and compute from centimeters to tens of nanometers, within a single manufacturing flow. Instead of continuously shuttling data between separate memory and processing units, data is stored and accessed locally, where computation happens.

This shift from data movement to data proximity unlocks a new baseline for AI system efficiency

• Significant performance gains by reducing memory access latency. 
• Drastic energy savings driven by minimized data transfer requirements.
• Lower infrastructure cost by reducing reliance on expensive external high-bandwidth memory.

Leveraging Europe’s deep-tech infrastructure
The 16nm pre-production chip will be manufactured at a commercial foundry, with the proprietary Vertical Integrated Memory layer added directly at imec. To achieve this, the partnership will utilize the capabilities of imec’s NanoIC pilot line, a major European Union-funded initiative designed to bridge the gap between advanced semiconductor research and industrial reality.

« The defining limit on AI scaling today isn’t processing power, it’s the exponential cost and energy of moving data » said Sylvain Dubois, co-founder and CEO of Vertical Compute. « Taking our Vertically Integrated Memory from a breakthrough concept to 16nm production requires world-class ecosystem alignment. Partnering with imec proves that we can build and scale the next generation of highly efficient AI infrastructure right here in Europe, providing global markets with the hardware needed to sustain the AI revolution.»

« The acceleration of AI demands paradigm-level innovation at the hardware level,» added Sri Samavedam, imec senior VP. « Vertical Compute’s approach to vertically integrated memory is exactly the kind of architectural shift the industry needs. By integrating our engineering teams and leveraging the NanoIC pilot line, we are accelerating the transition from frontier research to meaningful commercial deployment.»

A shift beyond incremental scaling
As AI continues to expand across industries and into edge environments, incremental improvements in existing architectures are no longer sufficient. This partnership represents a critical step in building a more efficient and accessible computing foundation, one where memory is no longer a constraint, but a tightly integrated part of the compute fabric.

This work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union’s Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit nanoic-project.eu.