Backside technology circuit boosters for SRAM scaling

The limited scalability of SRAM has become a significant barrier to meeting power and performance targets in modern compute systems. This challenge has driven the design community to explore a range of solutions, from hardware-level innovations to rethinking layout strategies and transistor architectures.

Recent advancements in CMOS technology, particularly backside technology, have opened new avenues for SRAM scaling. These innovations offer the potential to overcome the traditional Power-Performance-Area (PPA) trade-offs that have historically constrained SRAM design.

This PhD research aims to:

• Investigate the opportunities enabled by backside technology to scale SRAM memory systems for future high-performance computing, exploring concepts such as circuit-assist capacitors for power management and split-supply bitcells.
• Redefine the cost function of circuit-assist techniques in the context of backside-enabled SRAM scaling.
• Benchmark circuit-assist approaches against alternative bitcell architectures, such as read/write-decoupled designs (e.g., 8T cells or split-supply cells).

This work will leverage imec’s predictive PDK (A14 node and beyond) for backside technology to explore a broad spectrum of SRAM design optimizations, including:

• Read/write assist circuits
• Timing and signal routing enhancements
• Power delivery and management strategies

Complete SRAM memory circuits will be designed for PPA benchmarking. Selected key innovations will be taken to tape-out, with fabrication conducted via industry partnerships and/or imec’s internal technology platforms.