PhD - Leuven | Just now
CMOS2.0 challenges design-technology co-optimization research to look beyond pinpointing a complex device architecture with an optimal power, performance, and area (PPA) trade-off. Pathfinding research in the CMOS2.0 era requires not only meticulously tailoring trade-offs towards the envisioned application, but also diversifying trade-offs within one application. As different subcircuits within one application, e.g., a CPU, could benefit different trade-offs, enabling significant differences in technology within on application, addressing these trade-offs for subcircuits individually is key for pathfinding research.
Required background: Nanotechnology, Electrical Engineering or equivalent.
Type of work: 75% modeling/simulation/design, 25% literature
Supervisor: (to be defined/not in list)
Co-supervisor: (to be defined/not in list)
Daily advisor: Sheng Yang, Hannah Watson
The reference code for this position is 2026-217.