Advancing Ultrasonic Inspection for Voids in Heterogeneously Integrated Semiconductor Devices

The rapid evolution of semiconductor technology is increasingly driven by heterogeneous integration, where diverse components are combined within a single system to deliver enhanced performance, functionality, and miniaturization. Hybrid bonding and advanced stacking approaches—such as wafer-on-wafer, die-on-wafer, and die-on-die—allow for more functionality per unit area, enabling the next generation of high-performance computing, AI, and mobile devices. However, these complex integration schemes introduce significant manufacturing challenges, particularly regarding the integrity of the bonds and interconnects between stacked layers.

One critical concern is the formation of voids during the bonding process, akin to bubbles trapped under the screen protector of a cellphone. These voids can compromise electrical, thermal, and mechanical reliability. Additionally, the use of through-silicon vias (TSVs) for vertical interconnects—sometimes with large cross-sections (up to 10 × 100 μm²)—introduces additional risk of fill defects and void formation. Detecting these defects, especially within multi-tier and patterned structures, is crucial for yield and reliability.

Scanning Acoustic Microscopy (SAM) is a widely established technique for detecting bonding voids. SAM leverages the strong reflection of ultrasonic waves from pockets on entrapped air, making it effective for identifying large defects. However, as the size of the void decreases, the reflection on the voids also drops, reducing signal-to-noise ratio and making it more difficult to detect the void or to differentiate between voids and metal features. The challenge is exacerbated in multitier stacked structures, where signal intensity further diminishes. For TSVs, the situation is even more complex due to guided wave propagation in both silicon and copper, with propagation characteristics and intensity highly dependent on TSV dimensions and liner materials.

This project aims to improve the detectability of bonding and TSV voids in advanced semiconductor stacks using SAM operating in the 100 MHz–1 GHz frequency range. By developing a deeper understanding of ultrasonic propagation in both unpatterned stacks (for bonding voids only) and patterned structures (for TSV-related and bonding voids), the research will address current limitations in defect detection for heterogeneous integration.

The proposed work is structured in two main phases.

In phase 1, the selected candidate will design, fabricate and characterize test vehicles with programmed bonding and TSV voids. The designed bonding and TSV voids will have varying x-y-z dimensions and depths. The impact of metal interfaces and multi-tier stacking configurations will also be studied.  The test vehicles will also include patterned structures with TSVs of varying diameters, aspect ratios, and liner compositions. The acoustic inspections of these test vehicles will be combined with a fundamental study of the acoustic wave propagation, attenuation and reflections in these complex systems using numerical simulations. The goal is to develop a semi-quantitative model allowing the candidate to understand and predict the impact of all the critical parameters at stake during the SAM inspection of an advanced semiconductor device.

In phase 2, the understanding and model developed in Phase 1 will be used to improve void detectability in practical use cases of modern heterogeneously integrated devices such as die-to-wafer hybrid bonding or wafer-to-wafer hybrid bonding. This approach should allow to demystify the complex analysis of SAM inspection of such structures where so many parameters are at play and impact the grey levels of the obtained images.

This project will deliver new insights into the acoustic response of advanced semiconductor stacks and TSVs, leading to improved SAM methodologies for void detection. The findings will inform process control and quality assurance in heterogeneous integration, ultimately contributing to higher reliability and yield in next-generation semiconductor devices. The outcomes are expected to contribute valuable insights into process optimization and quality control, ultimately supporting continued innovation in semiconductor device fabrication. For this purpose, the candidate will also be immersed within the imec ecosystem of processing and metrology suppliers, thus exposed directly to the currently relevant challenges.