Digital SoC Design Engineer (temporary assignment)

We need you as a Digital IC Design Engineer to be part of our multidisciplinary team to: Define concepts and architectures for next generation ICs for IoT, edge AI accelerator ICs and Health applications ICs. Take responsibility for the design of high-performance, ultra-low-power digital signal processing modules.

The assignment

• Coming up with digital architectures. 
• RTL development for ASIC and FPGA. 
• Making trade-offs for minimal power consumption at best performance and low cost, while considering scalability, maintainability and re-usability. 
• Collaborate with digital back-end team for synthesis and physical implementation. 
• Verification. 
• Validate and characterize your own designs experimentally in a lab environment. 
• Collaborate in an inter-disciplinary team. 
• Understand (internal or external) customer needs, challenges and requirements and translate that into solutions that you can incorporate into your designs. 
• Contribute to high-quality reports and documentation.

Required knowledge and skills 

• MSc or PhD in electronics engineering with 5+ years of relevant experience. 
• Strong experience with digital circuit design in (System) Verilog is required. 
• Following application experience is a preferred: Affiliation on hardware efficient AI accelerator, event driven computing, compute modalities like multi-core -processor systems, in memory computing, large data computing. 
• Hardware modelling. Architecting and designing CPU and peripheral (sub-)systems. 
• Experience with digital verification is preferred: verification plan definition and tracking, verification methodologies, code-functional coverage, constrained random verification. 
• Understanding of the remaining steps of the digital ASIC-design flow is required: logic synthesis, timing analysis, power simulation, logic equivalence, DFT and-or P&R. 
• Experience with scripting languages like TCL, Matlab and Python is required. 
• Experience with revisioning systems, like git is required. 
• Knowledge of FPGA-development is a plus. 
• Knowledge of low-power designs is a plus. 
• Experience with Cadence IC design tools is a plus. 
• Experience with C and systemC is a plus. Structural way of working and ability to develop and manage activity planning is highly preferred. 
• Previous experience working closely with (internal or external) stakeholders is a plus. 
• Able to take initiative and responsibility for team’s success. 
• Thinking pro-actively, working independently and having a creative problem-solving attitude are attributes that define yourself. 
• Have broad interest across disciplines and like to embrace new challenges. 
• Excellent communication skills in English (written and spoken).

What we offer

• Duration of the assignment, 6 months, with extension if applicable
• Desired start date: 16/03/2026
• Work regime: full time

Location

We provide the flexibility to work both from our office premises and remotely from home. This to maintain a healthy work-life balance while being an integral part of our team. But an onsite presence of 3 days a week is required. It's not possible to work 100% remote. 

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