/Hardware-Efficient Analog Compressive Sensing IC for High-Density Neural Recording

Hardware-Efficient Analog Compressive Sensing IC for High-Density Neural Recording

PhD - Leuven | Just now

Developing analog/mixed IC that compresses and aggregates thousands of neural signals on-chip while preserving essential spike information.

Modern neuroscience and brain–machine interface research increasingly depend on high-density neural recording systems that capture activity from thousands of electrodes. These systems amplify, digitize, and transmit neural signals for analysis, yet growing channel counts expose hard constraints: enormous data bandwidth, strict power budgets to avoid tissue heating, and limited silicon area. Streaming raw data quickly becomes infeasible, and conventional compression schemes struggle to balance fidelity, latency, and energy efficiency. This motivates on-chip strategies that reduce data at the source without compromising the quality required for reliable spike detection. 

Imec is a world-leading research and innovation hub in nanoelectronics and digital technologies, leveraging its expertise in advanced semiconductor processes, system design, and AI to enable next-generation biomedical technologies, including neural interfacing and recording systems. The main goal of this PhD topic is to investigate and design a hardwareefficient analog compressive sensing integrated circuit (IC). By exploiting the sparsity of extracellular spikes, the approach transforms highdimensional neural data into a lowdimensional representation either before or during analog-to-digital conversion, significantly reducing bandwidth and energy per bit. Through codesign of the analog frontend with a signalcombination stage that aggregates multiple channels into a reduced set of outputs, the system retains critical spike timing and amplitude information while minimizing silicon area and power consumption. The candidate will model and investigate various compressing methods and design innovative chip prototypes that could achieve more than 10× datarate reduction at isoaccuracy compared to conventional neural recording chips, while ensuring robustness to multi-spike collisions and sensitivity to low-amplitude activity. The candidate will further contribute to the verification and electrical characterization of the prototypes under real-world biological conditions. 

Skills and background: 

  • Master’s degree (or equivalent) in Electrical Engineering, Microelectronics, Biomedical Engineering, Applied Physics, or a related field. 

  • Solid knowledge of analog and mixed-signal integrated circuit design with foundation knowledge of signal-processing theory and hardware algorithms. 

  • Experience with IC design and simulation tools (Cadence Virtuoso, Spectre, etc.). 

  • Knowledge of digital circuit design is a plus. 

  • Experience with bench evaluation and PCB design; FPGA/embedded firmware experience is a plus. 



Required background: Electrical Engineering

Type of work: 15% literature, 15% algorithms/modeling, 60% IC design, 10% experimental testing

Supervisor: Georges Gielen

Co-supervisor: Carolina Mora Lopez

Daily advisor: Yoontae Jake Jung, Xiaolin Yang

The reference code for this position is 2026-160. Mention this reference code on your application form.

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