Hetero-integration of two-dimensional electronic materials for active memory applications

The evolution of the next-generation computing critically needs significant improvement in On-chip memory, particularly in the AI-driven demand. In such a scenario, 2D semiconductors align naturally both at the device and the system levels. This is due to their superior transport properties that make better devices, while their molecularly thin nature and lower-temperature integration has inherent potential for 3D-stacked memory layers. In particular, implementation of basic memory cells such as the 2T0C DRAM in 2D semiconductors, taking advantage of the simultaneously high ON and OFF state performance is promising towards building high bandwidth memory. While proof-of-concept memory cells with 2D materials have been demonstrated, assessing their true potential requires significant research at the device and integration levels, some of the key aspects being scalability of performance, reliability, and practicality of integration. This Ph.D. proposal seeks to not only determine how competitive 2D materials-based DRAM can be in terms of performance and power, but also explore how to utilize key advantages of 2D materials in device ideas and applications for the future, particularly in digital memory. 

The broad questions this proposal seeks to address are the following: 

(a) Can we improve basic DRAM cells with 2D materials? 

(b) Which are the better 2D materials for DRAM? 

(c) How does the performance evolve with miniaturization; what are the scaling limits?  

(d) Does the performance improve significantly with 2D materials hetero-integrated with other device technologies, e.g. oxide semiconductors? 

(e) Are there any other memory cell architectures which can benefit significantly from 2D materials?