Unraveling Next-gen 3D NAND Flash Through Model-Driven Experiments

Memories are a fundamental component of all electronic systems. Non-volatile data storage is at the forefront of the electronics industry, representing over 80% of all transistors produced. Three-dimensional (3-D) NAND flash memory is the predominant non-volatile technology, being integrated into a broad array of applications, like mobile phones, personal computers, data centers, and artificial intelligence systems. Memory densities are continuously advancing; cutting-edge 3-D NAND flash technologies have achieved bit densities of 20 Gigabit per mm², with projections estimating 256 Gb/mm² by 2028. These high densities are obtained through vertically arranged cells that capture charge in a SiN layer [1].

Further improvement of 3-D NAND requires increasingly sophisticated gate-stack materials and cell designs. The operation of these cells depends on a complex interplay of charge injection, trapping, detrapping, and transport through the different layers of the gate stack. In a complete memory cell, these mechanisms occur simultaneously and influence one another, making it difficult to determine from electrical measurements which physical processes are responsible for the observed behavior. This challenge becomes even more important for emerging gate-stack technologies, such as advanced high-k dielectric stacks and next-generation charge-trap layers, where improvements in memory characteristics must be linked to their underlying physical origins.

The objective of this PhD is to develop a model-driven experimental methodology for identifying and quantifying the charge-trapping and transport mechanisms that govern 3-D NAND operation. Rather than relying solely on measurements of complete memory cells, simplified physical models will be used to predict electrical signatures that uniquely distinguish between competing physical explanations. These predictions will guide the design of dedicated capacitor test structures, enabling individual mechanisms to be investigated under carefully controlled electrical conditions.

As a PhD researcher, you will first perform a literature review to develop a deep understanding of charge trapping, charge transport, and memory operation in state-of-the-art 3-D NAND technologies. You will become familiar with both in-house and commercial simulation tools and use them to develop simplified physical models of advanced gate stacks. Based on these models, you will help design dedicated experiments and test structures that can isolate specific transport and trapping phenomena. The resulting measurements will be compared against model predictions, creating an iterative loop between simulation, experiment design, and characterization that progressively improves understanding of the underlying device physics.

Ultimately, this PhD topic aims to establish a physically grounded and experimentally validated framework for understanding advanced 3-D NAND gate stacks and predicting the behavior of future memory technologies. The project combines semiconductor device physics, computational modeling, experiment design, and electrical characterization. You will be embedded within imec's world-leading storage memory research program and interact closely with experts in modeling, integration, and characterization. Access to state-of-the-art experimental data, dedicated test structures, and advanced simulation tools will ensure that your research remains strongly connected to the development of future commercial memory technologies.

[1] S.S Kim et al. "Review of semiconductor flash memory devices for material and process issues." Advanced Materials, vol. 35. 43, 2200659, 2023.