/Impact of moisture on the reliability of 3-D & OIO technologies

Impact of moisture on the reliability of 3-D & OIO technologies

PhD - Leuven | More than two weeks ago

Moisture in microelectronics: myths or risk?

Since more than 50 years, corrosion of the metal lines in integrated-circuits, resulting from the presence of atmospheric moisture near the metal, is a serious reliability challenge [1, 2]. Traditionally, corrosion issues have been mitigated by the utilization of thick passivation stacks, consisting in an association of silicon nitride and silicon oxide, and preventing moisture from reaching the metal lines [3].

 

Nevertheless, in this new microelectronic era, where complex products are built by combining different chips, leveraging on new interconnect modules such as optical IO, and polymer based RDL technologies, more and more applications are incompatible with the classical passivation stacks. For example, at imec, silicon photonics chips require opening of the passivation layers to connect the optical fibers [4], resulting in the direct exposure of the underneath BEOL layers to atmospheric moisture leading to severe reliability concerns such as metal line corrosion [3] or waveguide mode shifting due to refractive index increase [5]. In the realm of 3D technologies, the introduction of novel materials such as polymers, molds or unprotected SiCN bonding layers for e.g., raises concerns of new moisture induced reliability issues. To guarantee reliable 3D technologies and products, the impact of moisture on the reliability of advanced packaging technologies must be assessed.

 

 

The aim of this PhD is to understand the risk posed by moisture uptake and its impact on the reliability performance of OIO and 3D interconnects. The degradation mechanisms induced by moisture uptake should be identified and understood to propose possible mitigation strategies. In more details, the following achievements are expected:

 

  • Comparison and selection of the most appropriate characterization methodologies to monitor moisture diffusion in dielectrics.
  • Characterization of the moisture diffusion kinetics in various materials (eg; SiN, SiCN, Polymers...);
  • Identification of the possible failure modes and their relative mechanisms for the different dielectric and polymer materials used in OIO and 3D technologies;
  • Assessing the impact of moisture on dielectrics and polymers electrical and optical performances;
  • Assessing the impact on the electrical and optical performances of waveguides and copper lines when surrounded by moisture exposed dielectric materials. 

 To reach these goals, the following activities are foreseen:

  • Deep understanding of the OIO & 3D technologies and their applications;
  • Building moisture diffusion models for the different dielectric & polymer materials used in OIO& 3D technologies
  • Electrical & optical characterization of moisture exposed dielectric & polymer materials.
  • Statistical data analysis of reliability data extracted from electrical characterization;
  • Building of analytical/computer models for dielectric & polymer lifetime predictions;
  • Interaction with OIO and 3-D process integration engineers to provide them feedback on the reliability characterization results.
  • Proposition of various mitigation strategies to build reliable products. 

Who you are:

  • You have a material sciences background and enjoy experimental work.
  • Prior experience with moisture diffusion in dielectric/polymer materials would be beneficial.
  • Deep knowledge of characterization methodologies such as ellipsometry or FTIR would be an asset.
  • Prior exposure to ellipsometry and FTIR spectrum analysis methodology is an advantage. 

 

[1] Frankenthal, R. P. & Becker, W. H., Corrosion Failure Mechanisms for Gold Metallizations in Electronic Circuits, Journal of The Electrochemical Society, Vol. 126, No. 10, 1979.

[2] Leppänen, J. et al., Aluminium corrosion in power semiconductor devices, Microelectronics Reliability, Vol. 137, 2022.

[3] Comizzoli et al., Corrosion of Aluminum IC Metallization with Defective Surface Passivation Layer, International Reliability Physics Symposium, 1980.

[4] He, J. et al., V-Groove assisted passive assembly of single-mode fibers to ultra-broadband polarization-insensitive edge couplers for silicon photonics, European Conference on Optical Communication (ECOC 2019).

[5] Y. Zhang, M. Cui, Refractive Index Sensor Based on the Symmetric MIM Waveguide Structure, J. Electron. Mater. 48 (2) (2019)


 


 

Required background: Material Sciences, Physics

Type of work: 40% Experimental, 20% Data analysis, 20% Literature, 20% Modeling and simulations.

Supervisor:

Co-supervisor: Kristof Croes

Daily advisor: Emmanuel Chery

The reference code for this position is 2025-183. Mention this reference code on your application form.

NanoIC logo

Who we are
Accept marketing-cookies to view this content.
imec's cleanroom
Accept marketing-cookies to view this content.

Related jobs

R&D Manager Lay-out and Design Support

Within Semiconductor Technologie Platforms, we are seeking an experienced and motivated R&D Manager to lead and coordinate a team of engineers specializing in IC layout design, tape-out, PDK and data preparation for photomask ordering. This critical role involves supporting depar

Silicon Photonics Integration Engineer

Imec is a global pioneer in developing integrated silicon photonics technology through its Optical I/O R&D program targeting short-reach optical communications. This technology is successfully offered via wafer-level prototype fabrication services to customers in telecom, datacom

EU / Funded Project Technical Coordinator

Combine advanced R&D, project execution and partner interface

Silicon Photonics Laser R&D Engineer

Join the 3D and silicon photonics team at imec’s R&D headquarters located in the heart of Europe and help in revolutionizing next-generation silicon integrated photonics.

Technical Account Manager

The Technical Account Manager (TAM) plays a pivotal role in cultivating strong relationships with our key customers. Its purpose is to maximize the value of imec’s offering in silicon processing services and low volume manufacturing.

Researcher – Backside Patterning and Litho Process Developer

As R&D Engineer Litho Process Development you will be a member of the ALP Compute Process Development team, part of the Angstrom Patterning department, and be responsible for the development and optimization of lithography processes requested by IMEC’s CORE programs and internal
Job opportunities

Send this job to your email