/Integrated Circuit Layout Engineer

Integrated Circuit Layout Engineer

Research & development - Gent | More than two weeks ago

Ghent University – imec IDLab Design group

Ghent University is one of the most important education and research institutions in the Low Countries, ranked 71 in the Academic Ranking of World Universities (http://www.shanghairanking.com/). On a daily basis, over 15,000 staff members and 49,000 students implement its motto "Dare to Think". Ghent University's mission statement is characterized by qualitative education, internationally renowned research and a pluralistic social responsibility. 

The IDLab research group is also a core group of imec. Imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. Imec is headquartered in Leuven, Belgium and also has distributed R&D groups at a number of Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. 

All of these particular traits make IDLab a top-class research employer.

Context

The IDLab-Design group, of Ghent University and imec have started significant integrated circuit design activities towards creation of IP blocks and prototype chips using highly scaled CMOS processes, including for example 5nm FinFET. The mask layout design in such highly scaled processes is challenging in nature and a highly skilled task. The level of difficulty is further increased if it concerns IP for high-speed and high-frequency operation.
 

What you will do

You will join a team of integrated circuit (IC) design researchers and layout engineers who are working towards realization of wireline DAC prototypes using scaled CMOS (e.g. 5nm FinFET), with following tasks and responsibilities:

  • Generate mask layouts according to specifications set forward by the team’s IC designers and layout engineers. 
  • Ensure the mask layouts pass standard verifications.
  • Provide feedback to the IC design team in terms of good design practices to ensure a smooth flow from schematic design to clean mask layouts.
  • Guide the team in terms of good layout practices.

What we do for you

The successful candidate will join an internationally renowned team of high-speed electronic integrated circuit designers. Training for completing mask layout tasks in some of the world’s most advanced semiconductor processes will be provided. He or she will also get the opportunity to learn other skills e.g. related to the existing ECAD environment, integrated circuit design, printed circuit board layout, soft skills etc.

Who you are

  • You have A Master degree or equivalent in the domain of electrical engineering, 
  • Deep knowledge of IC design tools such as Cadence is a must: you have at least 3 years experience in the realization and verification of mask layouts in recent FinFET or similar CMOS processes,
  • The nature of this position comes with a significant amount of responsibility, as the performance of high-speed, analog and mixed-signal integrated circuit blocks depends a lot on the quality of the chip layout and the collaboration between design and layout engineers. You are therefore by nature a meticulous person with a strong eye to detail and a real team player.
  • You feel comfortable handling multiple on-going tasks in parallel, if necessary against strict timelines.
  • You integrate well into a multi-cultured and diverse team, and you feel comfortable in the role of being a central part of the team, which will rely on you for critical layout work. 
  • You are a teamplayer that integrates will into a multi-cultured and diverse team, fluency in English is essential,
  • You are allowed to work in Belgium.

Interested?

Send your application or any questions concerning this vacancy to Peter Ossieur (peter.ossieur@imec.be)

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