[NanoIC] Circuit design exploration for quasi-adiabatic compute in the most advanced technology nodes

Circuits for quasi-adiabatic compute have already been proposed and demonstrated more than 30 years ago [e.g. M. Frank, PhD thesis MIT, 1999]. Researchers at that time demonstrated that those circuit designs enabled more energy efficient compute, but the area overhead and speed penalty was far too big to be applicable for mainstream compute.

Today, it is time to revisit the conclusions of 30 years ago. When using the most advanced state-of-the-art topologies, the area overhead and speed penalty will be substantially lower as it was 30 years ago. Moreover, local energy reservoirs can also be implemented much more efficient using state-of-the-art technologies.

The object of this PhD thesis is to investigate the most energy efficient circuit designs to be used in combination with all the possible  local energy reservoirs  that can be implemented in possible future CMOS back-end-of-line technologies. The obvious application is the reduction of the energy usage in high-performance compute in data centers for AI, while keeping an equal system performance.