Understanding the surface chemistry of amorphous carbon materials to enable area-selective atomic layer deposition on complex 3D integration architectures

As we approach the limits of nano-electronic device scaling, novel transistor architectures are needed to meet the demand of a smaller transistor footprint while maintaining high performance and low power. For advanced nodes beyond the 3 nm regime, several options have been proposed, including scaled nanosheet transistors and complementary field effect transistors (CFETs). The common theme in these approaches is to go from horizontal to vertical and three-dimensional (3D) architectures. For such structures, conventional patterning approaches face increasing challenges in terms of cost, complexity, sustainability and process variability. Area-selective deposition (ASD) has emerged as a promising bottom-up fabrication strategy capable of reducing lithography requirements by enabling material growth exclusively on predefined regions of a pre-patterned substrate.

As CMOS technology continues to evolve toward CFET and gate-all-around architectures, ASD is a key enabler for reducing integration complexity through material engineering. The research will focus on understanding how carbon-based growth-inhibiting surfaces, surface chemistry, and interface engineering influence the selective deposition of metal oxide dipole layers to provide different V_T flavours in the transistors, as shown in the Figure below. Particular emphasis will be placed on correlating carbon material properties (sp²/sp³ bonding ratio, C/H and O content, morphology, and surface functionalization) with the nucleation behavior of metal oxide dipole layers, selectivity, and electrical analysis. In parallel, the project will explore ASD approaches for the Al₂O₃ / HfO₂ cover spacer, where selective dielectric deposition on targeted surfaces can simplify patterning schemes for enablement of p- and n-type source/drain epitaxy. The work aims to establish the scientific foundations and process guidelines required for integrating selective dipoles and cover spacers into next-generation CMOS and CFET process flows.

This PhD aims to develop a fundamental understanding of growth inhibition mechanisms on carbon surfaces^1,2,3, quantify selectivity limits, and validate process integration routes relevant to semiconductor logic, memory devices, and heterogeneous integration. The final goal of this project is to treasure all the learning gathered on un-patterned surfaces to nano-scale 3D features where the growth and selectivity mechanisms are expected to be different with respect to planar surfaces, due to different incoming surface composition (after etching and post-etching clean) and due to topography/geometry effects. A great asset offered by Imec is the possibility of getting sub-20 nm patterned features because of cutting-edge technology, integration and state-of-the-art materials and 300 mm IC manufacturing equipment. The outcome is expected to provide both mechanistic understanding of ASD phenomena and practical solutions for future semiconductor manufacturing nodes.

You will join imec’s Materials and Interfaces, Deposition and Analysis (MIDA) department and benefit from its strong expertise in thin film deposition and epitaxy [4,5,6,7]. Your PhD research will take place at the interface of science and industrial innovation, with access to imec’s state-of-the-art cleanroom and characterization labs. You will enrich your competences via the KU Leuven PhD trajectory and the imec academy. You will share your results with industrial partners and the international research community and be part of a vibrant MIDA PhD community of around 30 students supported by scientists, engineers, staff, and professors. The topic potentially includes international collaborations with other academic groups.

¹ Ivan Zyulkov, et al., Mater. Adv. (2020); 1 (8): 3049–3057.

² Eric Stevens et al., Chemistry of Materials (2020) 30(10)

³M. Krishtab et al.,  ACS Appl. Mater. Interfaces (2021) 13 (27): 32381–32392