Routing criticality and sensitivity analysis in advanced CMOS nodes

Project description: 

This internship project presents an exciting opportunity for a passionate, curious, and results-oriented student to contribute to the advancement of semiconductor design, particularly in the context of routing congestion and criticality assessment. By understanding the influence of the Back-End-of-Line (BEOL, namely metal routing layers) stack on the routing congestion and the design PPAC (performance, power, area, cost), you will develop a new methodology to quantify routing criticality. The aim is to help digital designers optimize the BEOL stack selection process to improve the design PPAC, ultimately playing a vital role in shaping the future of semiconductor technology.

With contemporary designs featuring over 100 billion transistors, the sheer number of metal wires for connecting transistors is on a similar order of magnitude, presenting a formidable routing challenge. To address this complexity, modern Electronic Design Automation (EDA) tools leverage heuristics and complex optimization algorithms to complete the routing task while meeting the design criteria (performance, design rule constraints, etc.) as good as possible. After the routing is completed, however, the billions of wires pose a daunting challenge for designers to conduct any in-depth analysis on the routing quality. Hence, it is difficult to establish a direct link between the criticality of wiring resources and chip performance. The motivation of this project is to fill this gap to analyze the interdependencies among routing resources, routing congestion, and design PPAC, and eventually develop a comprehensive methodology to study the routing criticality.

Project Objectives:

In this project, you will collaborate with the researchers within the Physical Design Research (PDRS) team to analyze the impact of different BEOL stacks on the routing and PPAC of the designs. The insight into these analysis results leads to a new quantitative methodology for evaluating the criticality of routing resources. This methodology aims to offer a more comprehensive assessment of routing congestion and will eventually facilitate the optimization of the BEOL stack, tailored to the design's unique characteristics.
Project Tasks:

1. Literature Review: Conduct a thorough review of existing research in the field of routing congestion evaluation and criticality assessment to identify gaps and potential avenues for innovation.
2. Performance Evaluation: Perform experiments on generating physical designs with different BEOL stacks to comprehend their influences on routing criticality and PPAC of designs.
3. Method Generalization: Explore the possibility of generalizing the methodology to assess the routing criticality and PPAC impact.
4. Methodology development: Work with the PDRS team to design and implement a quantitative methodology that effectively evaluates the criticality of routing resources within designs.
5. Documentation and Reporting: Produce detailed documentation of the developed methodology, its application, and the findings from performance evaluations. Generate clear and concise reports for sharing with the semiconductor industry.

Requirements to fulfil this project: 

• Understanding of CMOS technology
• Understanding of digital circuit design flow (Place and Route)
• Knowledge of Linux 
• Communicative and active team player
• Analytical thinking, affinity to problem solving
• Prior experience in EDA tools is a plus
• Programming skill in Python, Tcl, shell is a plus

We invite motivated students to join us in this endeavor, where you can make a meaningful impact on the semiconductor industry while gaining valuable experience in semiconductor design and innovation. Are you ready to be part of the future of advanced semiconductor design? Join us and be a part of the transformation in this exciting field.

Type of Project: Combination of internship and thesis 

Master's degree: Master of Engineering Science; Master of Engineering Technology; Master of Science 

Duration: 6 months 

Master program:  Electrotechnics/Electrical Engineering; Nanoscience & Nanotechnology 

For more information or application, please contact Ji-Yung Lin (ji-yung.lin@imec.be) and Francesco Dell Atti (francesco.dellatti@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.