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Study of Dep/Etch Cycling Process for High Aspect Ratio Etch
Master projects/internships - Leuven | Just now
HAR etch for CFET applications
Idea is to etch HAR structures (~1:20) (very rough overview) meeting criteria as below
- Vertical Profile
- Selectivity to Gate Protective layer(s)
- Critical Dimension (CD) requirement
- Uniformity within Wafer and Pitch
Type of Project: Internship
Master's degree: Master of Science; Master of Engineering Technology
Master program: Nanoscience & Nanotechnology; Electrotechnics/Electrical Engineering; Chemistry/Chemical Engineering; Physics
Supervisor: Stefan De Gendt (Chemistry, Nano)
For more information or application, please contact the supervising scientist Subhobroto Choudhury (subhobroto.choudhury@imec.be).