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Study of Dep/Etch Cycling Process for High Aspect Ratio Etch
Master projects/internships - Leuven | Just now
HAR etch for CFET applications
Idea is to etch HAR structures (~1:20) (very rough overview) meeting criteria as below
•Vertical
Profile
•Selectivity
to Gate Protective layer(s)
•Critical
Dimension (CD) requirement
•Uniformity
within Wafer and Pitch
Type of project: Internship
Required degree: Master of Science, Master of Engineering Technology
Required background: Nanoscience & Nanotechnology, Electrotechnics/Electrical Engineering, Chemistry/Chemical Engineering, Physics
Supervising scientist(s): For further information or for application, please contact: Subhobroto Choudhury (Subhobroto.Choudhury@imec.be)