/Understanding the limitations of a sequential CFET flow in terms of thermal budgets

Understanding the limitations of a sequential CFET flow in terms of thermal budgets

Master projects/internships - Leuven | Just now

Explore the impact of imec’s technology solutions on tomorrow’s computer architectures
  • CFET architectures are considered one possible solution to drive Moore’s Law forward beyond traditional scaling. However, the 3D stacking of complementary transistor functionality brings along novel challenges in device integration and engineering. This internship focuses on modelling thermal behavior in novel CFET device structures. You will be working with integration, device, and simulation engineers to learn about state-of-the-art device design and fabrication, and carry out simulations to understand thermal effects in these nanoscale structures to guide thermal management.


Type of project: Internship

Duration: 3 months

Required degree: Master of Engineering Technology, Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology, Physics

Supervising scientist(s): For further information or for application, please contact: Philippe Matagne (Philippe.Matagne@imec.be)

Imec allowance will be provided.

Who we are
Accept marketing-cookies to view this content.
imec's cleanroom
Accept marketing-cookies to view this content.

Send this job to your email