Thermal-aware design of advanced interconnects for future technologies

The back-end-of-line (BEOL) is a complex wiring scheme that distributes clock and other signals, provides power and ground, and transfers electrical signals from one transistor to another. The demand for advancements in Artificial Intelligence (AI) / Machine Learning (ML) training and High-Performance Computing (HPC) capabilities results in an ongoing scaling of transistors and the accompanied introduction of scaling boosters. As dimensional scaling of the transistors continues, BEOL dimensions are also being reduced – leading to ever smaller metal pitches and reduced cross-sectional areas of the wires. Combined with the introduction of materials with low dielectric constant and low thermal conductivity or even air gaps to improve the electrical performance, this results in a higher BEOL thermal resistance and makes the interconnect lines more susceptible to self-heating due to Joule heating. In advanced package assemblies for AI or HPC applications, the BEOL becomes the dominant contributor to the thermal resistance, limiting further computer capabilities advancement.

The objective of this PhD is to assess the thermal bottlenecks in the BEOL stacks and optimize the BEOL thermal performance for future technology architectures. You will build upon the extensive available in-house knowledge on BEOL thermal modeling and experimental characterization and interact with design and technology experts to develop thermal mitigation solutions that can be implemented and demonstrated in test vehicles through design improvements and the introduction of new materials.

In this PhD work, the following activities are foreseen:

• Thermal modeling of advanced BEOL technology node and scaling boosters.
• Apply the developed thermal models to realistic scenarios to assess the impact of different technology and design options in collaboration with the BEOL technology community.
• Investigate the role of the interfaces between the different metals inside the BEOL stack and for the connections between the metals and the transistors.
• Assess the potential of the introduction of new material options, such as 2D materials or materials with high thermal conductivity, to reduce the interface thermal resistance or improve lateral heat spreading.
• Design thermal test structures for the experimental characterization and model validation. New methodologies might need to be developed to accurately characterize the thermal properties of the investigated features.