Indium-gallium-zinc-oxide (IGZO)-based two-transistor n-capacitor (2TnC) dynamic random-access memory (DRAM) cells are excellent candidates for analog in-memory computing.
They can accomplish the inference phase of machine learning applications much more efficiently than what is possible today.
In this article, the authors show how IGZO-based 2T1C and its capacitor-less variant (2T0C) can be optimized for high retention time. They demonstrate the possibility of multilevel programming and multiply accumulate operations – important steps towards industrial adoption.
This article was published in Planet Analog.
Subhali Subhechha is a senior researcher of memory devices at imec, Belgium. She received her Bachelor’s and Master’s degrees in electrical engineering from Indian Institute of Technology Kanpur. She has been working on different memory devices with imec, Belgium, since 2013. In 2019, she received her Ph.D. in electrical engineering from KU Leuven, Belgium, working on selectorless resistive switching memories. Her current interests are design, modeling, and characterization of oxide semiconductor memories, 3D DRAM, novel memory concepts, and neuromorphic computing. She has served as a member of technical committees in IEDM and IPFA
Attilio Belmonte is the program manager of active memory at imec, Belgium, where he manages projects related to various memory devices, namely (3D)DRAM, OTS selectors, and FeRAM. He joined imec in 2011 and received his Ph.D. in Physics from KU Leuven, Belgium, in 2015, with a dissertation on novel CBRAM devices. As a researcher, he explored several emerging memory devices, mainly focusing on RRAM, oxide semiconductors, and alternative high-K dielectrics for DRAM. He authored and co-authored more than 85 journal and conference publications.
Gouri Sankar Kar received his Ph.D. in semiconductor device physics from the Indian Institute of Technology, Kharagpur, India, in 2002. From 2002 to 2005, he was a visiting scientist at Max Planck Institute for Solid State Research, Stuttgart, Germany. In 2006, he joined Infineon/Qimonda in Dresden, Germany, as lead integration engineer and was responsible for vertical transistor development for the DRAM application. In 2009, he joined imec, Leuven, Belgium, where he is currently working as the VP memory (DRAM, MRAM, FeRAM, NAND etc.) and as the Program Director Exploratory Logic (MX2 FET and CNTFET).
19 October 2023