Article interconnects/thermal aspects
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Mitigating the thermal bottleneck in advanced interconnects

A modeling framework to accurately predict heat dissipation in the chip’s back-end-of-line


As dimensional scaling continues, the heating of the interconnects in the chip’s back-end-of-line (BEOL) has become a growing concern, as it can compromise the chip’s reliability.

Imec presents a modeling framework that accurately predicts heat dissipation in advanced BEOL structures, considering the coupling with the logic cells in the front-end-of-line (FEOL) and boundary conditions from packaging technologies.

This article discusses the model and its added value. Valuable insights are presented, such as the dominant contribution of low-k dielectrics and via layers to the BEOL’s thermal resistance.