Article ESD protection
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How to protect advanced CMOS technologies with thin Si substrates against ESD events

Imec exploits the chip’s functional backside to develop high-performance ESD protection devices


On-chip ESD protection devices are critical to the reliability and yield of various electronic products.

Their protective capabilities may, however, be affected by every new technology that enters the semiconductor technology roadmap.

This article illustrates the detrimental effect of Si substrate thinning – characteristic for backside power delivery networks and advanced 3D integration technologies – on the ESD device performance and heat dissipation.

To address the issue, the authors propose alternative ESD protection devices that exploit the wafer’s active functional backside to enhance ESD performance.