The existing memory hierarchy in computer systems can be further improved by adding a new memory class that fills the DRAM-NAND gap: storage class memory. Densely packed resistive RAM (RRAM) arrays – an emerging memory based on resistive switching – is a promising candidate to help fill this gap. But so far, the implementation of high-density RRAM lags behind. One of the important reasons were sneak current issues in the high density 4F2 architecture. One way to suppress this parasitic leakage is to add a so-called two-terminal selector that connects serially with each resistive memory element in a 4F2 configuration. At VLSI 2017, imec proposed a novel selenium (Se)-based selector that displays characteristics closely compliant with the required two-terminal selector for storage class memory application. In this article, Gouri Sankar Kar, Distinguished Member of Technical Staff at imec, discusses the challenges for implementing a selection device, and highlights the importance of imec’s new thermally stable germanium-selenium (GeSe)-based selector.
Storage class memory: filling the gap between DRAM and NAND Flash
The future memory landscape requires a new class of memory that is able to fill the gap between dynamic random access memory (DRAM) and NAND Flash memories in terms of density, cost and performance: the storage class memory. This new memory class should allow massive amounts of data to be accessed in a very short time. Gouri Sankar Kar: “Most probably, more than one novel memory technology will be required to span the entire gap."