Semiconductor technology & processing

15 min

The 3D FeFET: contender for 3D-NAND Flash memory and machine learning

The recent discovery of a ferroelectric phase in hafnium-oxide (HfO2) has raised renewed interest from industry in ferroelectric-based memories. An example of such a memory is the non-volatile HfO2-based ferroelectric field-effect transistor (FeFET), showing interesting properties for 3D-NAND-like storage applications and in-memory computing. Jan Van Houdt, Scientific Director at imec, explains how the FeFET works and how this exciting ‘newcomer’ might fit in the next-generation memory landscape.

The ferroelectric FET: a transistor with a memory

Ferroelectrics are a class of materials that consist of crystals exhibiting spontaneous electrical polarization. They can be in two states, which can be reversed with an external electric field. When such a field is applied, the electric dipoles formed in the crystal structure of the ferroelectric material tend to align themselves with the field direction. After the field is removed, they retain their polarization state – giving the material its non-volatile characteristic. A ferroelectric material has a non-linear relationship between the applied electric field and the polarization charge, giving the ferroelectric polarization-voltage (P-V) characteristic the form of a hysteresis loop.

Ferroelectric materials are being explored for DRAM-like memory applications – with ferroelectrics implemented as the dielectric in the DRAM capacitor. But one can also think of replacing the gate dielectric of a standard high-k/metal-gate transistor with a ferroelectric and end up with a non-volatile transistor: the ferroelectric FET or FeFET. The two stable, remnant polarization states of the (now ferroelectric) gate insulator modify the transistor threshold voltage, even when the supply voltage is removed. Accordingly, the binary states are encoded in the threshold voltage of the transistor. Writing of the memory cell can be done by applying a pulse on the transistor’s gate which alters the polarization state of the ferroelectric material and impacts the threshold voltage. For example, applying a positive pulse lowers the threshold voltage and leaves the cell in an ‘ON’-state. Reading is done by measuring the drain current. This type of memory operation resembles the working of a NAND Flash memory cell – where electrons are forced in and out of a floating gate, impacting the threshold voltage of the floating gate transistor in a similar way.

From dream to reality...

Discovered more than five decades ago, ferroelectric memory has always been considered ideal, due to its very low power needs, non-volatile character and high switching speed. However, issues with complex ferroelectric materials have presented significant challenges. Early attempts were based on ferroelectric materials belonging to the perovskite family of lead-zirconate-titanate (PZT). But conformally depositing these materials in thin layers has proven very challenging. Also, the very high dielectric constant of these materials (in the order of 300) posed an obstacle for integrating them into a functional transistor.

The recent discovery of a ferroelectric phase in hafnium-oxide (HfO2), a well-known and less complex material, has however triggered a renewed interest in this memory concept. Researchers discovered an orthorhombic crystal phase – the ferroelectric phase – that can be stabilized by doping HfO2 with e.g. silicon (Si). Compared to PZT, HfO2 has a lower dielectric constant and can be deposited in thin layers, in a conformal way. On top of that, HfO2 is a well-understood material that has been used as the gate stack dielectric material in logic devices. By cleverly modifying this CMOS-compatible material, the logic transistor can now be turned into a non-volatile FeFET memory transistor.

... and from planar to vertical

Functional FeFETs have already been demonstrated in two-dimensional, planar architectures. But the ability to make conformal layers of HfO2 opens the door towards vertical varieties, e.g. by depositing the ferroelectric material on a vertical ‘wall’ and stacking the transistors in the third dimension.

On the material side, these 3D FeFETs can solve some of the challenges imposed by 2D FeFET structures. One challenge has to do with the poly-crystalline nature of the HfO2 dielectric. Scaling the dimensions of the HfO2 layer significantly limits the number of crystal grains within the layer. Not all these grains have the same polarization direction, and this impacts their response on the external electric field – leading to large variabilities. By going 3D, this restriction is at least removed in the third dimension, relaxing the variability and allowing a better control of the statistics.

Vertical FeFET technology fits in a 3D-NAND-like manufacturing flow, an approach which has been actively pursued by imec. 3D-NAND Flash is today’s mainstream medium for high-density data storage. 3D NAND is relatively cheap and non-volatile, but it has a complex structure and slow memory operation.

Schematic representation of a 3D-NAND Flash structure.

Schematic representation of a 3D-NAND Flash structure.

These vertical FeFETs are expected to present several advantages over complex 3D-NAND Flash memories, including more simplified processing, lower power consumption and higher speed. Compared to 3D-NAND Flash, vertical FeFETs can potentially be programmed at much lower voltages (at about 4V compared to 20V for NAND), which leads to improved reliability and scalability.

First results: 2V memory window and Flash-like endurance

Since several years, imec is focusing on 3D-NAND-like vertical FeFETs, hereby using its longstanding experience in advanced 3D-NAND Flash technology development combined with the tools, background and vehicles developed for earlier research on PZT-based ferroelectric memories. Since 2016, imec and its partners have an industrial affiliation program running on vertical FeFETs.

In the frame of this program, the team tackles main challenges related to the processing, characterization and reliability of the 3D FeFET. For example, the imec team is building up the know-how on how to stabilize the orthorhombic phase of HfO2, which is the ferroelectric phase. This phase can be obtained by substitutional doping of the HfO2 layer with for example Si. This generates a strain in the thin layer, bringing the crystal into the desired orthorhombic phase. Si is preferred as a dopant atom because of the thermal budget (i.e., to preserve the ferroelectric phase), but the team also studies alternative dopants such as aluminum (Al) and lanthanum (La), and investigates the use of hafnium-zirconium-oxide as an alternative ferroelectric.

Recently, imec demonstrated a first functional vertical ferroelectric HfO2 FET based on a 3D macaroni NAND architecture. The device was fabricated based on imec’s process flow for 3D-NAND Flash memories, now replacing the typical oxide-nitride-oxide (ONO) dielectric layer by an 8nm Si-doped HfO2 layer – which is deposited using atomic layer deposition (ALD). Poly-Si is used as the gate material, and amorphous Si for the channel. The test vehicle contains a vertical string of three gates in series (a control gate, and a bottom and top selector gate). The hole in the string is filled with oxide and then recessed, giving it a macaroni-like structure. In a real 3D-NAND-like device, the number of control gates can mount up to 64 in the vertical direction to obtain a high-density memory solution.

(Left) Schematic cross-section of the macaroni-type 3D FeFET with three cells in series; (right) TEM cross section (Ø: 100nm).

(Left) Schematic cross-section of the macaroni-type 3D FeFET with three cells in series; (right) TEM cross section (Ø: 100nm).

For this test vehicle, up to 2V memory window was obtained after applying 100ns program/erase pulses. The FeFET exhibits 85°C retention: after 100 hours at 85°C, a clear separation of states can still be observed. The team also reported Flash-like endurance of 104 cycles and has performed first reliability assessments. Charge trapping – caused by high fields over the interface – is put forward as the limiting factor for the cycling performance. A decrease of the interface layer thickness could potentially address this challenge.

Memory characterization: up to 2V memory window was obtained after applying 100ns program (PRG)/erase (ERS) pulses.

Memory characterization: up to 2V memory window was obtained after applying 100ns program (PRG)/erase (ERS) pulses.

Reliability characterization: Evolution of the threshold voltage VT with cycling after program and erase. Closing of the memory window is observed after 104 cycles.

Reliability characterization: Evolution of the threshold voltage VT with cycling after program and erase. Closing of the memory window is observed after 104 cycles.

3D-NAND-like applications and machine learning

FeFETs are still in the early stages of R&D and it’s too soon to say if or when they will ever make it into production. Nevertheless, this promising new memory concept has raised major interest from the industrial players. It is the role of imec to explore its full potential and offer its partners a head start in this exciting research area. They can then decide how to best fit FeFET memories in their products and chips.

As a standalone memory, FeFETs are believed to enter the family of storage class memories (SCMs) and as such help closing the gap between fast, volatile DRAM and slow, non-volatile and high-density NAND Flash memories. FeFETs are non-volatile and can offer several advantages over NAND Flash: they have faster switching speeds, are simpler to process, consume less power and can potentially operate at much lower voltages. But, although closer to DRAM in terms of speed, the limited cycling performance (104 for FeFET compared to 1012 for DRAM) will most probably push FeFETs to the NAND side of the DRAM-NAND gap.

FeFET memories have also gained interest among the logic foundries: the memory’s high speed can be very advantageous for machine learning applications, which rely on in-memory computing. For this, several types of memories, including Flash, magnetic random access memory (MRAM), resistive RAM, phase change memory (PCM), static RAM (SRAM) and FeFET, are currently being explored. The non-linear characteristics and speed properties of FeFETs make the technology particularly appealing for machine learning applications that make use of deep learning convolutional neural network models. For this application, we will most probably see planar versions of FeFETs coming up.

Outlook: towards higher density FeFETs

A particular advantage of NAND-Flash technology is the ability to store up to 4 bits per cell, which gives the technology its unique high data density. In a traditional single-level cell, each cell can be in one of two binary states, storing one bit of information per cell. Industrial NAND-Flash cells have evolved from single-level cells to cells with 2, 3 and even 4 bits per cell. With 4 bits, the cells use 16 discrete charge levels in each individual transistor – requiring a sufficiently large memory window.

For FeFETs, imec sees three ways to increase the data density and make FeFETs true competitors for NAND Flash in terms of density. First, provided that the threshold voltage can be sufficiently stabilized, the 2 – 2.5V memory window of FeFETs should in principle allow programming 2 bits per cell – which requires 4 charge levels within the transistor.

Second, the cell density can be doubled by using a trench-like architecture for connecting the transistors, with two transistors on each side of the trench. In current 3D FeFET designs, such as in imec’s macaroni NAND architecture, the control gate is designed in a gate-all-around (GAA) structure. This means that the gate is wrapped around the channel, limiting the number of transistors (per layer and per string) to one. The GAA structure is needed in NAND Flash memories to improve the injection of charges into the floating gate or the nitride trapping layer but is not needed for FeFETs. Imec is currently exploring the use of an alternative trench-like structure, where the transistors are implemented at the sidewall of a trench – with two transistors now at opposite ends of the trench. This type of structure should potentially allow to double the cell density and to decrease the variability between cells.

And third, the FeFET memory cell can potentially be scaled to much smaller physical dimensions. In a typical NAND Flash cell, the ONO dielectric layer has a thickness of about 20nm. In a FeFET cell, the HfO2 ferroelectric layer is expected to scale down to 4nm. In addition, in the vertical direction, the lower operation voltage of the FeFET compared to NAND Flash will allow the word lines to come closer together.

In summary, these possible routes towards higher density in combination with a higher speed, non-volatility, Flash-like endurance, lower operation voltage and lower power consumption make 3D FeFETs interesting contenders for 3D-NAND-like applications.

Want to know more?

  • The paper ‘Vertical ferroelectric HfO2 FET based on 3D NAND architecture: towards dense low-power memory’ by K. Florent et al. was presented at the 2018 IEDM conference, and can be requested via our contact form.
  • If you want more information on ferroelectric memories, you can request the following papers via our contact form: (1) ‘Memory technology for the terabit era: from 2D to 3D’, Symp. on VLSI Technology, Kyoto, Japan, June 2017, invited, p. T24-25; (2) ‘3D memories and ferroelectrics’, 2017 IEEE-IMW, Monterey, CA, invited, p. 92-94.

About Jan Van Houdt

Jan Van Houdt received a Ph.D. from the KU Leuven. During his PhD work, he invented the HIMOS™ Flash memory, which he transferred to several industrial production lines. In 1999, he became responsible for Flash memory at imec and as such was the driving force behind the expansion of imec’s Industrial Affiliation Program on Memory Technology. Jan has published more than 300 papers in international journals and accumulated more than 250 conference contributions (incl. ~50 invitations and 5 best paper awards). He has filed about 80 patents and served on the program and organizing committees of 10 major semiconductor conferences. In 2014, he received the title of IEEE Fellow for his contributions to Flash memory devices. In the same year, he started the Ferroelectrics program at imec and became a guest professor at the KU Leuven teaching on CMOS and memory technology. Today, he is Scientific Director at imec, active both in the memory as well as in the logic scaling programs.

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