Advanced-nodes SRAM Variability

This MSc project targets a physics to circuit methodology for SRAM bitcell variability that starts at the TCAD level, incorporates parasitic extraction (PEX), and culminates in a compact model (CM) model card suitable for fast circuit analysis. You will (i) build a TCAD variability space that includes process parameters (e.g., V_TH shifts, interface traps, contact resistivity, RDF proxies) and geometry knobs (e.g., L_G, spacer thickness, W/H of fin/nanosheet, contact enclosure), (ii) generate PEX aware netlists per variation point to capture FEOL/BEOL coupling and realistic RC loading, and (iii) extract bitcell KPIs—static noise margin (SNM), write/read margins, delay, energy, and retention sensitivity—under correlated/global and local/mismatch conditions. This PEX aware variability treatment follows internal DTCO frameworks showing that PEX must be recomputed whenever geometry/process perturbations are applied, rather than reusing a single nominal RC view, to avoid biased variability conclusions.

On top of the physics grounded dataset, you will create a compact model parameterization flow: map TCAD/PEX outcomes to CM knobs (e.g., mobility vs. field, subgap trap terms, gate leakage parameters, DIBL/SCE tunes, self heating scalars) and produce a model card ensemble that reproduces the KPI distributions across PVT. To make this ensemble usable by designers, an ML assisted layer will provide (a) interpolative surrogate predictors (e.g., Gaussian process regression or regularized regressors) that estimate KPIs and/or CM parameters at unseen points inside the validated variability domain, and (b) dimensionality reduction (e.g., PCA) that compresses the model card space into a few orthogonal latent factors with minimal loss of KPI fidelity, yielding a “simulation friendly” reduced model card. The deliverable is a validated, PEX aware, ML compressed model card plus scripts/notebooks to regenerate predictions, aligned with ongoing PDK/DTCO flows for logic and memory.
 

Type of Internship: Internship; Combination of internship and thesis; Master internship; Thesis

Master's degree: Master of Science; Master of Engineering Science

Required educational background: Electrotechnics/Electrical Engineering

Duration: >5 months

For more information or application, please contact the supervising scientists Arvind Sharma (Arvind.Sharma@imec.be), Dawit Abdi (Dawit.Abdi@imec.be), Pieter Weckx (Pieter.Weckx@imec.be) and Dishant Sangani (Dishant.Sangani@imec.be).