Analysis of Single event-upsets (SEUs) in IGZO based eDRAM

This activity will develop TCAD simulation frameworks to evaluate single event effects (SEE) in IGZO based eDRAM cells, where the ultra low leakage and bias sensitive threshold behavior of IGZO devices make them particularly susceptible to transient charge deposition. The work will model how a single energetic particle strike generates localized charge, induces transient conduction paths, perturbs the storage node voltage, and potentially triggers soft errors through momentary loss of retention or corrupted sensing margins. By incorporating device level material parameters, defect state dynamics, and realistic circuit biasing, the simulations will quantify critical SEE mechanisms such as single event transients, storage node upset, and recovery behavior in both 2T0C and 3T0C bitcells. The goal is to build predictive insight into how isolated radiation hits translate into memory corruption events and to identify device  and circuit level design levers for improving robustness under SEE dominated environments.
 

Type of Internship: Internship; Combination of internship and thesis; Master internship

Master's degree: Master of Engineering Science; Master of Science

Required educational background: Electrotechnics/Electrical Engineering

Duration:  >5 months

For more information or application, please contact the supervising scientists Arvind Sharma (arvind.sharma@imec.be) and Aishwarya Singh (aishwarya.singh@imec.be).