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Alleviating Thermal Challenges In Angstrom Nodes: Paving The Way For 3D Integrated Circuits (3D-ICs) of The Future
PhD - Leuven | Just now
Cool Chips, Hot Tech: Designing Thermally-Efficient 3D ICs for the Angstrom Era
Background & Motivation:
As semiconductor scaling enters the Angstrom era, power density increases exponentially while thermal dissipation becomes increasingly constrained—particularly in 3D integrated systems leveraging chiplet-based or vertically stacked designs. Emerging paradigms such as CMOS 2.0 and heterogeneous integration (e.g., separate tiers for logic, SRAM, PDN, and I/O) offer significant performance-per-Watt benefits, but exacerbate thermal bottlenecks across die-die and die-package interfaces.
While traditional EDA thermal tools provide first-order estimates, they fail to capture the fine-grained spatial and transient behaviors critical at these advanced nodes. Furthermore, the complex performance-power-area-temperature (PPAT) trade-offs introduced by thermal mitigation strategies (e.g., thermal vias, liquid cooling, advanced materials) are poorly understood from a cross-technology co-optimization (DTCO/STCO) perspective.
Objective:
This PhD aims to quantify, model, and mitigate thermal bottlenecks in Angstrom-node 3D-ICs using a cross-layer, multi-physics approach. The specific objectives include but not limited:Thermal Hotspot Characterization: Use imec’s Angstrom-node PDKs and realistic workloads to extract localized power maps, and analyze the spatio-temporal evolution of thermal hotspots. Focus on transient thermal behavior and dynamic interactions between stacked tiers.
You will work in imec’s interdisciplinary environment, collaborating across thermal modeling, PDK development, system architects, and EDA tool vendors. The position is embedded in imec’s DTCO and STCO programs.Multi-Scale Thermal Modeling: Extend imec’s internal physical design and simulation framework to support hierarchical thermal modeling: from die-level layouts to package cross-section. Explore multi-resolution meshing, transient simulation speedups, and runtime-accuracy trade-offs.
Thermal Mitigation & Design Exploration: Evaluate thermal-aware floorplanning, thermal through-silicon vias (T-TSVs), high-conductivity interposers, and cooling cavity fills (e.g., diamond, mold, microchannels). Quantify their PPAT impact via comparative case studies.Co-Optimization Methodology: Develop a holistic system-technology co-optimization (STCO) flow that integrates thermal constraints early in architecture and packaging design. Propose reusable EDA-friendly optimization techniques for early design closure.
Environment:
Candidate Profile:
Master’s degree in Electrical Engineering, Computer Engineering, Applied Physics, Microelectronics, or similar.Solid knowledge of physical design, computer architecture, microelectronics, thermal simulation, and/or system-level modeling.
Experience with EDA tools such as Cadence, Comsol, ANSYS, or similar is a plus.
Interest in cross-layer co-optimization, multi-physics analysis, and practical tool development.Required background: Electrical Engineering, Applied Physics, Microelectronics, Computer Engineering
Type of work: 80% modeling/simulation, 20% literature
Supervisor: Dragomir Milojevic
Daily advisor: Yukai Chen, Matthew Walker
The reference code for this position is 2026-048. Mention this reference code on your application form.