Cell-Aware vs. Small Cells

No integrated circuit (IC) manufacturing process is flawless, so all ICs must be tested for manufacturing defects to ensure adequate product quality for customers. Advances in semiconductor technologies have enabled the integration of more gates with smaller feature sizes into a single IC, making ICs increasingly prone to numerous, subtle defects. Furthermore, ICs are now widely used in safety-critical applications like automotive, avionics, and medical domains, where undetected faults ("test escapes") are unacceptable. Consequently, the semiconductor industry seeks to enhance IC manufacturing test quality while retaining benefits like high fault coverage and automated diagnosis through automatic test pattern generation (ATPG).

Eichenberger et al. [1] identified that many test escapes result from undetected cell-internal defects, as traditional stuck-at ATPG only targets faults in between cells. Cell-aware testing (CAT) is a two-step test generation approach that also targets these cell-internal faults. In Step 1, potential defect locations are identified for each cell based on its layout, followed by detailed analog simulations to determine which cell-level test patterns detect which defects. The results are stored in a binary defect detection matrix (DDM) for each library cell, with columns for defects and rows for patterns. An entry (d,p) is marked as ‘1’ if and only if pattern p detects defect d. Step 2, cell-aware ATPG, is performed per chip design and involves expanding cell-level test patterns into core- or chip-level patterns through ATPG propagation and justification. The expansion's success is guaranteed, as it depends on the circuit environment of the cell-under-test [Zhao et al., ITC’19].

CAT is particularly effective for circuits containing large and complex standard cells with many inputs. These cells have a greater number of cell-internal potential defect locations and more cell-level test patterns to choose from. CAT specifically addresses these additional faults by embedding cell-level test patterns that detect them into the chip-level test pattern set. In contrast, CAT has minimal impact on small one- or two-input library cells, as they have few cell-internal defect locations, and the corresponding faults are usually covered already by one of their few cell-level test patterns necessary for external faults.

Large and complex standard cells can be constructed from small one- or two-input library cells. However, large complex cells are designed to be more area-efficient than implementing the same function using smaller cells with fewer inputs. Can we quantify this area advantage? If large, complex standard cells are broken down, their cell-internal defects become cell-external and thus detectable by regular stuck-at ATPG. Are the fault coverages from these two approaches identical? Can they be addressed with the same test patterns? Are these two methods of test pattern generation fully equivalent—CAT with large and complex cells in the netlist versus regular stuck-at ATPG applied to a netlist where large cells are decomposed into small, simple ones?

We are seeking a student in Computer Science, Informatics, or Electrical Engineering with excellent or high academic performance and a keen interest in learning about design-for-test (DfT) for digital integrated circuits (ICs). While deep knowledge of semiconductors is not a prerequisite, proficiency in at least one programming language (C++, Python) and English is essential, as imec is an international organization where English is the primary working language.