Design exploration platform for multilayer chip architectures

Traditional chip designs, build as planar architectures face increasing challenges in meeting the requirements for AI applications due to power dissipation, interconnect bottlenecks, and limited scaling. To address these challenges, this research fits into imec’s CMOS2.0 project to explore novel multi-layer, three-dimensional chip architectures that

leverage heterogeneous integration of different technology nodes. By stacking multiple layers of processing elements, memory, and specialized accelerators, the proposed approach aims to improve computational performance while reducing power consumption and footprint.

This Ph.D. work focuses on developing an Exploration Platform to simulate and optimize multi-layer chip architectures. The first phase involves constructing this platform, enabling simulation experiments with layer stacking, interconnect structures, and power performance trade-offs. The second phase researches interconnect modeling, essential for efficient routing and communication across layers. The third phase introduces a rudimentary placement and routing algorithm, demonstrating three-dimensional chip

layout.