N2/A14 Gate-leakage and second-order effects | N3/N5 FF CM Calibration

This work will focus on building and calibrating physics informed compact models for nanosheet and CFET platforms at the N2/A14 nodes. Given the extremely strong bias temperature dependence, the CM effort will explicitly include gate leakage mechanisms (including temperature dependent tunnel currents), and second order effects such as mobility degradation, V_TH shifts under bias stress, and self heating interactions with nanosheet/CFET thermal environments. Model extraction will rely on TCAD to CM parameter flow, incorporating multi bias datasets, transient retention behavior, and variability distributions.

This work will develop compact models tailored for N3/N5 FinFET peripheral logic and memory driving circuits, ensuring accurate prediction of device performance under advanced-node constraints. The CM development will incorporate gate induced drain leakage (GIDL), short channel effects, drain induced barrier lowering, self heating, bias temperature instability driven V_TH drift, and second order conduction mechanisms needed for high fidelity transient and retention simulations. Calibration will be based on measured FinFET characteristics across voltage, temperature, and stress operating spaces, ensuring robust reproduction of switching behavior, leakage profiles, and variability. These refined models will enable co optimization of memory peripherals, sensing paths, and timing margins for next generation CMOS 2.0 circuitry.
 

Master's degree: Master of Engineering Science

Duration: >6months. 5 months per sub-topic (N2/A14 Gate-leakage and second-order effects | N3/N5 FF CM Calibration )

Required educational background: Electrotechnics/Electrical Engineering

University Promotor: Stefan De Gendt (Chemistry, Nano)

For more information or application, please contact the supervising scientists Arvind Sharma (Arvind.Sharma@imec.be) and Dishant Sangani (Dishant.Sangani@imec.be).