PhD - Leuven | More than two weeks ago
Over the past half-century, the performance, the transistor density, and the size of the chips have constantly increased. With the advent of AI, automotive self-driving, high-performance computing, and mobiles that have become as powerful as some portable computers, there are no signs that the demand for functionality and computing power will slow down soon.
An increase in die size and performance comes with thermal and thermo-mechanical challenges at the packaging level due to residual stresses generated during the fabrication, power dissipation, and/or temperature variations. Inside a chip package, the silicon dies are integrated with other materials like organic substrates, solder interconnections, underfills, and overmold. These materials have different stiffness and Coefficients of Thermal Expansion (CTE), resulting in a mismatch responsible for stress build-up, which may lead to reliability issues such as fractures or cracks in the chip or the interconnections. Among the different possibilities to reduce the risk of failure, we can mention three categories: (1) material selection to reduce CTE mismatch of the materials and the effect of processing temperatures. (2) improve thermal management to limit temperature variation, and (3) develop new interconnection designs such as flexible interfaces acting as a buffer layer.
This Ph.D. topic will investigate innovative solutions for flexible interfaces, such as flexible interconnections. These solutions are fundamental for the future of chip integration, in particular in the context of chiplet for automotive and high-performance computing.
What you will do:
Required background: Engineering Science
Type of work: 65% modeling/simulation, 25% experimental, 10% literature
Supervisor: Clement Merckling
Daily advisor: Nicolas Pantano, Mario Gonzalez
The reference code for this position is 2024-003. Mention this reference code on your application form.