PhD - Leuven | More than two weeks ago
Vertical stacking of integrated circuits, known as the 3-D integration, has emerged as a breakthrough solution to overcome the limitations of traditional continuous scaling of planar devices. 3-D integration enables superior performances with reduced system sizes. Moreover, it improves the system heterogeneity while reducing the processing complexity by separately fabricating the chips with different functionalities (e.g., memory and logic). Among several 3-D integration schemes, wafer-to-wafer hybrid bonding is distinguished as the key technology to achieving high-density interconnections required for fine-partitioning 3-D system-on-chip applications. In this bonding technology, both wafers are finished with a dielectric layer with embedded Cu pads. The wafer pair is then aligned face-to-face with a small vertical distance between them, on the order of a few tens of micrometers. The top wafer is pushed through a localized area at its center to establish the initial contact between wafers. The bonding is then propagated in a wave-like pattern due to the interaction forces between opposing wafers.
A major challenge associated with this process is acquiring a sufficiently low alignment error between the bonded wafers, for which the current and future industry demands are extremely stringent. It is not a trivial task to meet these demands since the final alignment is affected by various parameters, some of which can be listed as: wafer properties (shape, residual stress, mechanical properties), the dielectric material choice, extrusion/recession of Cu pads, the chuck design holding the wafers, the bonding recipe, initial distance between wafers, the magnitude of the point contact force, adhesion forces between dielectrics, air viscosity and gravitational effects. Considering the presence of numerous parameters and their potential interactions, optimization attempts that only focus on experimental approaches will have limited capabilities due to their slow-paced and expensive nature. Therefore, it is necessary to develop supplementary methodologies based on simulation techniques.
The purpose of this PhD topic is to deepen the understanding on both the physics of bond-wave propagation and the impact of mechanical boundary conditions using modeling and simulation techniques. To achieve this, the PhD student will develop a physics-based mechanical modeling environment (based on the finite-element method) to study the bonding phenomena. Modeling activities will first be initiated using simplified 2-D axisymmetric models, which will later be extended to full 3-D wafer bonding simulations. Where possible, bond wave metrology data along with experimental information will be provided to calibrate the simulations. The learnings obtained through simulations will be utilized to guide the industry and academia in terms of wafer preparation and bonding configurations.
This PhD topic is situated at the core of semiconductor technology, where the student will have a chance to interact with and gain exposure to diverse teams and programs at imec such as metrology, processing, patterning and reliability. The student will be provided with training on modeling tools and get a chance to collaborate with various experts from different fields.
This position is best suited for candidates from an engineering background with a keen interest in physics-based mechanical modeling and an affinity for cross-team collaborations.
Required background: M.Sc in Materials Science and Engineering, Mechanical Engineering, Physics or equivalent
Type of work: 60% simulations, 20% experimental, 15% data analysis, 5% literature
Supervisor: Clement Merckling
Co-supervisor: Mario Gonzalez
Daily advisor: Oguzhan Orkut Okudur
The reference code for this position is 2024-001. Mention this reference code on your application form.