/Integration and Simulation of Cutting-Edge Memory Models for Compute-near-Memory

Integration and Simulation of Cutting-Edge Memory Models for Compute-near-Memory

Master projects/internships - Leuven | More than two weeks ago

Examining the role of new memory technologies to help overcome memory wall issues in CnM-enabled systems

Alternative memory technologies are being examined for viability at the main memory-level as a means to either reduce power, reduce area, or increase performance in a wide variety of systems. Numerous candidates, such as various kinds of MRAMs, FerroRAMs, and 3D-stacked RAMs, have emerged in the technology domain to address common limitations in traditional memories. However, their trade-offs are yet to be examined at the system level in the presence of logic near the memory.
In this internship, you will learn how to use imec’s system-level framework for examining novel memory technologies and compute-near-memory (CnM) processing cores. You will then model the aforementioned technologies to extrapolate high-level power, performance, and area statistics in a variety of application scenarios that utilize CnM processing cores.
Key responsibilities will include:

  • Learning and using DRAM simulators to model novel memory technologies and protocol.
  • Collaborating with technology teams to validate memory models.
  • Performing power and area analysis using Catapult HLS tools.
  • Examining new CnM target applications.

This role is ideal for someone who is deeply interested in hardware-software codesign, electrical engineering, and working in an interdisciplinary environment that values innovation, creativity, and real-world impact.

Profile: You are analytical and detail-oriented, with a strong interest in memory technologies and their impact on high-level applications such as AI, genomics, databases, forecasting, or other datacentre-class algorithms. You are adept at or have a keen interest in high-level synthesis, programming, and modelling.

Background: Computer engineering, electrical engineering, memory, accelerators. Knowledge of SystemC, Catapult tools, and/or scripting languages is an advantage.

Type of Project: Internship; Thesis 

Master's degree: Master of Engineering Science; Master of Science; Master of Engineering Technology 

Duration: 3 - 9 months

Master program: Electrotechnics/Electrical Engineering 

Supervising scientist(s): For more information or application, please contact Joshua Klein (joshua.klein@imec.be) and Leandro M. Giacomini Rocha (leandro.m.giacominirocha@imec.be)

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