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Study of 2D Nanosheet FET/ CFET for sub-1 nm node
PhD - Leuven | Just now
Explore different routes to introduce 2D NS-FET/CFET in the logic scaling roadmap.
While fundamental research keeps providing new device insights and understanding in material processing, 2D-materials has emerged as a promising alternative to Si for driving the logic scaling roadmap forward [1-2]. Ab-initio modelling predicts semi-conducting transition metal dichalcogenides (TMD) being interesting candidate materials for transistors with ultimate gate length scaling [3]. Additionally, insight studies are pointing in the direction of nanosheet device architectures [4]. Inspired by silicon technology, the roadmap for 2D FET channel is moving from planar design towards nanosheet FETs (NS-FETs) and eventually 2D complementary FETs (CFETs) [5-7]. However, many challenges remain to unlock their incorporation into the Si-technology, especially the contact module at the source/drain area in a Field-Effect Transistor device [8-9]. It is important to verify experimentally the potential of such a device and identify key parameters determining the overall performance.
In this project, the PhD candidate will explore different routes to realize 2D NS-FET/CFET for advanced nodes. This work requires a double approach. The experimental workflow contains the fabrication of the nanosheet stacks and the development of specific process steps. The device will be fabricated in imec's XPLORE LAB with a lab-2-fab approach i.e., keeping CMOS compatibility central. Also, detailed electrical device characterization is required. Correlation of these finding with other inspection techniques contributes to the overall understanding of device operation. This performance assessment will help the modelling team to further elaborate on the models.
[1] D. Akinwande et al., Nature 573,507–518 (2019) [2]. Verreck, D., ISSCC, pp. 26-28, 2023. [3]. A. Afzalian et al, SISPAD (2019). [4] Ahmed et al, IEDM 2020. [5] Y.Y. Chung, IEDM, pp. 34-5, 2022. [6] F. Xi, IEDM, pp.1-4, 2024. [7] C.J. Dorow, IEDM, pp. 7-5, 2022. [8]. T. Schram, Advanced Materials 34.48 (2022): 2109796. [9] K.P. O’Brien, nature communications 14.1 (2023): 6400.
In this project, the PhD candidate will explore different routes to realize 2D NS-FET/CFET for advanced nodes. This work requires a double approach. The experimental workflow contains the fabrication of the nanosheet stacks and the development of specific process steps. The device will be fabricated in imec's XPLORE LAB with a lab-2-fab approach i.e., keeping CMOS compatibility central. Also, detailed electrical device characterization is required. Correlation of these finding with other inspection techniques contributes to the overall understanding of device operation. This performance assessment will help the modelling team to further elaborate on the models.
[1] D. Akinwande et al., Nature 573,507–518 (2019) [2]. Verreck, D., ISSCC, pp. 26-28, 2023. [3]. A. Afzalian et al, SISPAD (2019). [4] Ahmed et al, IEDM 2020. [5] Y.Y. Chung, IEDM, pp. 34-5, 2022. [6] F. Xi, IEDM, pp.1-4, 2024. [7] C.J. Dorow, IEDM, pp. 7-5, 2022. [8]. T. Schram, Advanced Materials 34.48 (2022): 2109796. [9] K.P. O’Brien, nature communications 14.1 (2023): 6400.
Required background: Master in Physics/ Materials Science/Nanotechnology/ Electrical engineering; Theoretical understanding of, and experience with material physics, electron device physics; Nanofabrication and Cleanroom experience is a plus
Type of work: 40% experimental, 30% characterizations, 20% data analysis and simulation, 10% literature; Reporting and publishing of results in leading scientific journals and conferences.
Supervisor: Clement Merckling
Co-supervisor: Kaustuv Banerjee
Daily advisor: Fengben Xi
The reference code for this position is 2026-126. Mention this reference code on your application form.