Pathfinding advanced 2D pFET nonplanar device architectures
PhD - Leuven | Just now
Abstract:
Scaling of conventional planar CMOS technology is facing physical and material limitations, challenging the continuation of Moore’s law. As short-channel effects, leakage currents, and variability increasingly degrade device performance at nanoscale dimensions, exploration of alternative non-planar device geometries is a must. Nonplanar architectures - including FinFETs, gate-all-around (GAA), nanosheets, and nanowires - offer enhanced electrostatic control, reduced leakage, and improved scalability compared to their planar counterparts. The adoption of these three-dimensional device structures is therefore essential to sustain transistor density growth, performance improvements, and energy efficiency in future technology nodes.
Thinning the Si-channel thickness poses however additional challenges, due to a dramatic impact on mobility. On the other hand, 2D materials are envisioned to provide an alternative to Silicon channel in future CMOS technologies, and extend Moore’s law validity, thanks to their large electron and hole mobilities, achievable at an atomic-scale thin channel, which also provides superior electrostatic control. Their inclusion in mainstream technologies remains however an enormously challenging task, which requires creative device engineering and technology innovations, fundamental material understanding, as well as physical understanding of the mechanisms governing their electrical performance and reliability.
This work will focus on nonplanar gate-all-around device architectures with 2D transition metal dichalcogenide (TMD) channel, addressing the need to extend Moore’s law, identifying, developing and testing viable options for the realization of 2D-channel (stacked) nanosheet devices, and will explore paths towards realization of 2D-channel Complementary FET (CFET) devices. The device fabrication work will primarily address p-type channel specific constraints, with WSe2 as a leading candidate material, whenever applicable, for example for the development of contacts, gate stack or tuning of doping. You will propose, run and validate concept device flows, and will critically assess their compatibility with fab-based processes, as the concepts maturate. Extensive physical characterization and electrical testing are key aspects of this work – to enable validation of the concepts and assessment of the electrical device performance towards application specs. Use of various simulation packages, including e.g. process/device simulators, or of data analysis environments will be valuable tools at hand to support your work.
A lab-2-fab approach will enable the transfer of most successful innovations in fab processes, providing a realistic assessment of their viability. From this perspective, your work will build on and inter-relate with internal know-how, and benefit from the in-house knowledge and leading expertise of imec in the field of 2D materials and devices.
Profile:
We are looking for an enthusiastic person with a background/MSc degree in physics, electrical engineering or materials science, to join our team and work on exploratory logic devices. Furthermore, you:
- Have hands-on experience in nanodevice fabrication or previous exposure to it
- Are familiar with CMOS technology, device simulation or data analysis tools, as important assets
- Have solid theoretical knowledge and very good understanding of the device/2D materials physics
- Are willing to publish your best results in top-level conferences and/or high-impact journals in the field
- Are a self-driven person, able to work independently, while placing your work in the context of a larger team effort and organization’s strategic needs and priorities
- Are able to think out-of-the-box and can easily approach areas outside your comfort zone
- Can adapt and are able to reconsider your approach dynamically, while taking into account concurrent/new developments; you strive for the best
- Can work in an interdisciplinary team, including device and process engineers, simulation and reliability experts, materials scientists; are engaged, dependable and flexible
- Have good communication, presentations and writing skills; like working in an international and multicultural environment; are fluent in English
References:
- A. Penumatcha et al: High mobility TMD NMOS and PMOS transistors ang GAA architecture for ultimate CMOS scaling, IEDM Tech. Dig. 2023.
- Y.Y.Chung et al: “Monolayer-MoS2 Stacked Nanosheet Channel with C-type Metal Contact”, IEDM Tech. Dig. 2023.
- T.D. Ngo et al: The critical role of 2D TMD interfacial layers for pFET performance, IEDM Tech. Dig. 2024.
- M. Jaikissoon et al: Record PMOS WSe2 GAA performance using contact planarization, and systematic exploration of manufacturable, high-yield contacts, VLSI Tech. Symp. 2025.
- T.D. Ngo et al: Towards a low-disorder pFET gate stack for monolayer WSe2 channels, Proc. IEDM Tech. Dig. 2025 (to appear).
Required background: Electrical engineering, Physics, or Materials Sciences
Type of work: 50% device fabrication, 30% electrical characterization, 10% physical characterization, 10% literature
Supervisor: Nadine Collaert
Co-supervisor: Bogdan Govoreanu
Daily advisor: Bogdan Govoreanu, Tien Dat Ngo
The reference code for this position is 2026-181. Mention this reference code on your application form.