/[NanoIC] Reliability of semiconducting oxides: the last roadblock for memory applications

[NanoIC] Reliability of semiconducting oxides: the last roadblock for memory applications

PhD - Leuven | Just now

What if a new generation of transistors could help overcome some of the fundamental scaling limitations of today's memory technologies?

Amorphous oxide semiconductor (AOS) thin-film transistors, and particularly InGaZnO (IGZO), are promising candidates for enabling further DRAM scaling [1] and the increasingly heterogeneous architectures envisioned by the CMOS 2.0 revolution [2]. Their electrical performance is already impressive. However, one major challenge remains: reliability. Recent studies have shown that Bias-Temperature Instability (BTI) is currently one of the mechanisms limiting the lifetime of IGZO transistors [3,4]. We know that these devices degrade. But why?

 

The goal of this PhD is to uncover the physical mechanisms responsible for BTI in IGZO transistors and use this knowledge to make them more reliable for future memory applications.

 

The project will combine advanced electrical experiments, physics-based modelling, and microscopic simulations. The student will develop dedicated electrical characterization methods at imec and investigate how IGZO transistors degrade under different electrical and temperature conditions. The experimental results will then be combined with state-of-the-art device simulations and in-house modelling tools to identify the defects responsible for degradation and understand how microscopic processes translate into measurable device behavior.

 

The ultimate goal is to develop a comprehensive physics-based framework capable of describing and predicting IGZO degradation over a wide range of operating conditions. But understanding the problem is only half of the story. The insights obtained from the experiments and simulations will be fed back into the device fabrication and process development, allowing the student to identify strategies for improving IGZO reliability and ultimately demonstrating better-performing devices. In short, the project follows a powerful cycle: measure → understand → model → optimize → improve.

 

This is a genuinely multidisciplinary project at the intersection of semiconductor physics, materials science, device engineering, modelling, and reliability. The student will gain hands-on experience in:

  • Advanced semiconductor device characterization
  • Scientific programming and data analysis
  • Physics-based device modelling and simulation
  • Defect physics and degradation mechanisms
  • Microscopic/atomistic modelling of semiconductor materials
  • Semiconductor device and process technology

 

The project also offers the opportunity to work closely with device and process engineers, ab-initio modelling researchers, reliability experts, and industrial partners within the imec research environment.

 

This PhD is an opportunity to work on a technology that could contribute to the next generation of memory and computing systems, while tackling the problem that currently limits its deployment. You will not simply characterize a transistor. You will investigate what happens inside the material, develop the models needed to explain it, and use that knowledge to build more reliable devices.

 

If you are excited by the combination of physics, experiments, programming, and modelling—and by the possibility of discovering something genuinely new—this PhD is for you.


 

 

We are looking for a curious and motivated young researcher with a background in semiconductor physics, solid-state physics, materials science, or electrical engineering.

Programming experience in Python, MATLAB, Perl, C/C++, or similar languages is an advantage. Most importantly, we are looking for someone who enjoys asking “why?”, is excited by open scientific questions, wants to learn across disciplines, and is motivated to turn unexpected experimental results into new scientific insights.

 

[1] A. Belmonte, S. Kundu, S. Subhechha, A. Chasin, N. Rassoul, et al. “Lowest IOFF < 3 × 10− 21A/mm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT”. In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). 2023, pp. 1–2. DOI: 10.23919/VLSITechnologyandCir57934.2023.10185398.

[2] J. Ryckaert, S. B. Samavedam. “The CMOS 2.0 revolution”. Nature Reviews Electrical Engineering, 1(3), 139-140, 2024. Doi: 10.1038/s44287-023-00016-3

[3] A. Chasin, J. Franco, K. Triantopoulos, H. Dekkers, N. Rassoul, et al. “Understanding and modelling the PBTI reliability of thin-film IGZO transistors”. In: 2021 IEEE International Electron Devices Meeting (IEDM). 2021, pp. 31.1.1–31.1.4. DOI: 10 . 1109 / IEDM19574. 2021 .9720666

[4] A. Chasin, J. Franco, S. Van Beek, H. Dekkers, A. Kruv, et al. “Unraveling BTI in IGZO Devices: Impact of Device Architecture, Channel Film Deposition Method and Stoichiometry/Phase, and Device Operating Conditions”. In: 2024 IEEE International Electron Devices Meeting (IEDM). 2024, pp. 1–4. DOI: 10 . 1109 / IEDM50854 . 2024 . 10873388.


 


 


 

Required background: Electrical Engineering, Physics

Type of work: 70% experimental, 30% modelling

Supervisor: Kristof Croes (KU Leuven)

Co-supervisor: Kristof Croes (KU Leuven)

Daily advisor: Adrian Vaisman Chasin

The reference code for this position is 2027-027. Mention this reference code in your application.

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