Towards High-Endurance fast-erase 3D FeFETs with OSC channel

Ferroelectric field-effect transistors (FeFETs) based on hafnium-zirconium oxide (HZO) and oxide semiconductor (OSC) channels are among the most promising candidates for high-density embedded and standalone non-volatile memories. However, achieving ultra-high endurance (>10¹⁰ cycles), fast erase operation, and excellent device uniformity remains a major challenge, particularly in emerging 3D architectures. The underlying physical mechanisms responsible for memory-window degradation, endurance loss, and erase limitations are not yet fully understood.

This PhD project aims to identify and mitigate the fundamental reliability bottlenecks of HZO-based FeFETs with OSC channels. In this research, you will investigate which are the mechanisms behind the endurance degradation; and at the same time, you will explore device-stack optimization, process integration improvements, and advanced program/erase schemes. Particular attention will be dedicated to the understanding of the slow erase dynamics arising from the lack of hole carriers in oxide semiconductors, and to the proposal of novel channel materials and interface-engineering solutions to overcome these limitations. The behaviour of FeFETs under realistic array operation will also be assessed through dedicated experiments on both individual devices and memory arrays.

The work will combine advanced electrical characterization, targeted reliability experiments, physical analysis, and physics-based modeling to establish clear links between device performance and degradation mechanisms. By providing a comprehensive understanding of reliability limitations and proposing practical mitigation strategies, the project will contribute to the development of next-generation 3D FeFET memories with improved endurance, speed, and scalability.

What will you do?

• Characterize ferroelectric devices electrically, from standard tests to custom experiments, to enable a comprehensive evaluation of device performance.
• Design and perform targeted experiments to shed light on the physical mechanisms underlying device behaviour
• Model the operation and reliability of ferroelectric memory technologies.
• Translate your findings into design insights, proposing improvements for the next generation of devices.

Who are you?

• A physicist, nanoscientist/engineer, or electrical/electronic engineer.
• Solid knowledge of semiconductor physics.
• Skilled in programming and data analysis.
• A proactive problem solver and a strong team player.

Type of work:  15% literature, 65% measurement, 20% modelling.

Promotors:  Maarten Rosmeulen, Jan Van Houdt

Daily advisors:  Nicolo Ronchi

Further readings:

(1) Z. Chen et al., IEEE IEDM 2024, doi: 10.1109/IEDM50854.2024.10873449

(2) Z. Chen et al., IEEE VLSI 2026, doi: 10.1109/VLSITechnologyandCir65830.2026.11577259