[NanoIC topic] In-Operando Photoemission: Advancing Semiconductor Characterization

As semiconductor devices relentlessly shrink to the atomic scale, the complexities of their surfaces and interfaces take on a decisive role in determining performance, reliability, and longevity. In this landscape, understanding the intricate interactions between materials and electrical behaviour at the most fundamental level becomes essential for progress. Among the array of analytical tools available to researchers, photoemission stands out as a powerful technique, offering unparalleled sensitivity to the chemistry and electronic structure of surfaces and interfaces.

Photoemission techniques, rooted in the principles of the photoelectric effect, enable to probe the binding energies of core levels and valence bands. The connection between these material properties and actual device performance is, however, complex. Traditional electrical measurements—such as capacitance-voltage (CV)—have long been used to extract key parameters like effective work function (WF_eff), flat band voltage (VFB), effective oxide thickness (EOT), and the distribution of charges and dipoles within the gate stack. However, these approaches often require fabricating multiple test devices and rely heavily on prior assumptions about device structure and processing conditions. Such practices can be time-consuming and may obscure subtle, process-dependent effects that directly influence device behaviour.

Photoemission, especially when performed in-operando, promises a more direct and versatile approach to device characterisation. By analysing changes in energy levels as a function of applied bias and device architecture, researchers can discern the impact of process variations, material selection, and stack engineering on the fundamental electronic properties governing device operation. Yet, measuring these properties is not without challenges. The act of probing itself can induce changes in the device’s charge state, leading to energy shifts and potential misrepresentation of the true band structure. Grounding both the device gate and the silicon substrate can mitigate these effects to some extent, but more refined strategies—such as applying a controlled, non-zero bias to achieve flatband conditions—are necessary for accurate and reproducible results across different gate stack configurations.

The focus of this internship is to participate in the development of in-operando photoemission for advancing our understanding of semiconductor technologies. For this purpose, we have been recently acquiring a biasing system to be combined with our high-energy photoemission system (Ulvac-PHI Quantes) and to apply it to high-k metal gate development, a cornerstone for modern complementary metal-oxide-semiconductor (CMOS) devices.