/PhD Position in Design enablement for active back-side and early exploration flows for System-Technology Co-Optimization (STCO) in 2.5D/3D IC

PhD Position in Design enablement for active back-side and early exploration flows for System-Technology Co-Optimization (STCO) in 2.5D/3D IC

Leuven | About a week ago

Cadence Design Systems is looking for Employee - PhD Student, to work jointly with imec in the context of the STCO research program. PhD candidate will be located at imec, Leuven, Belgium, but will be enrolled as PhD student at Université libre de Bruxelles (ULB), Belgium.

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Cadence Design Systems

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com

What you will do

Together with Cadence R&D team, PhD candidate will work on physical design enablement (place & route) of the active back-side, starting with the correct understanding and formulation of the technology specifications. Design enablement per se will include the development of appropriate algorithms and methods implemented on top of the existing place & route tool. These will be then used for system-level characterization, first at block and then eventually at SoC level. The analysis will be carried out to capture system architecture-technology trade-offs. Further, the candidate will work on high-level exploration framework based on 3Dblox standard. The objective here is to enable System Technology Co-optimization early in the design cycle. The emphasis here is less on the design flow enablement and more on the interaction between system architecture design, 2D/3D technology (including active back-side) & partitioning choices. For example, the candidate will study & characterize data movements in complex SoCs assuming current & future 5.5D technology options with tuneable communication and memory specifications to propose up to date energy, delay & latency envelopes of future systems.

Topic

Future ICs will most likely combine CFET based standard cells in a plane with active silicon back-side, multiple active layers on the front side of a single die, and multi-die packages in 5.5D with vertical and lateral interconnect. Such advanced node technology assumptions are quite disruptive, not only with respect to the physical design tools, but also with respect to the system architecture design and implementation/technology trade-offs. While current physical implementation tools enable 3D system partitioning, they do that on coarse granularity level (memory or functional blocks), allowing the use of the existing place & route engines, modified to understand different types of 3D interfaces in different tool sessions. Obviously, much finer system partitioning at die level, involving multiple active layers can’t benefit from the above-mentioned methods & tools. Further, multi-layered dies can be stacked to create 3D chiplets that will be integrated in multi-die packages causing significant increase of the design space size. The use of state-of-the-art 3D enabled place & route, power, and thermal simulation tools to explore different architecture parameters, technology options and partitioning strategies is out of the question due to complex set-up and run-time for reasonably sized designs.

Who you are

You hold a Master of Science degree in electrical engineering or equivalent. You possess strong knowledge in digital electronics & digital system design, including HDL modelling, simulation, synthesis and physical design back-end flow (FPGA and/or ASIC). You are well versed into general programming environements (Linux, Python, C/C++ etc.).
You combine a strong interest in engineering and scientific research with a desire to see your work applied in industrial and academic collaborations. You are able to learn quickly and independently. You aspire to become an expert in your field, while simultaneously collaborating with other researchers and senior staff to efficiently generate state-of-the-art results.
You combine a strong interest in engineering and scientific research with a desire to see your work applied (in industrial, academic or (N)GO collaboration). You are able to learn quickly and independently. You aspire to become an expert in your field, while simultaneously collaborating with other researchers and senior staff to efficiently generate state-of-the-art results.