Realizing uniform quantum dot arrays for quantum computing through wafer scale characterization

Electron spins trapped in gate-defined semiconductor quantum dots are a promising platform for quantum computing. The long quantum coherence times and the compatibility with standard CMOS processes make silicon spin qubits one of the leading candidates for fault-tolerant quantum computers. To achieve this long-standing goal, a global research effort is underway to increase qubit count and device uniformity targeting large arrays comprising of millions of qubits, an essential step for enabling quantum error correction algorithms.

Arrays of quantum dots hosting electron spin qubits can be fabricated using state-of-the-art integrated circuit technologies. However, significant material, device, and process engineering challenges must still be addressed to achieve the level of uniformity required for large-scale systems. Due to current device variability, tuning the gate voltages of even modest arrays can be time-consuming and typically requires expert intervention. While AI-assisted tune-up methods could help streamline this process, scaling to arrays of several hundred qubits remains a substantial challenge.

In this PhD project, you will participate in imec’s silicon quantum computing program to address the challenges of upscaling silicon spin qubits. The goal of this project is to investigate and identify the relevant sources of quantum dot variability like strain, material defects, etc. and evaluate possible mitigation strategies encompassing process and materials exploration. To accomplish these goals, an advanced wafer-scale cryogenic testing platform will be developed. You will explore the technological challenges (mechanical, thermal) associated with the cryogenic characterization of single wafers and you will develop robust  measurement methodology for the extraction of Quantum Dot device parameters with statistical relevance. This study will help the evaluation and mitigation of noise and disorder sources and will be the basis of optimized integration flows targeting large Quantum Dot arrays.