High density SRAM scaling for next generation AI ​

Data-intensive applications such as AI and machine learning demand significantly higher on-chip memory capacity, often exceeding hundreds of megabytes, alongside more advanced memory management strategies. However, current SRAM technologies face major bottlenecks due to excessive cell leakage and the energy cost of data movement across ultra-large memory macros. These challenges hinder SRAM’s scalability to meet the capacity and efficiency requirements of next-generation systems.

This PhD research aims to:

• Investigate the fundamental CMOS technology and device-level limits for SRAM beyond the A14 technology node
• Establish the theoretical relationship between static and dynamic energy in SRAM as capacity scales to ultra-large regimes
• Develop key technology and circuit-level innovations to break the traditional Power-Performance-Area (PPA) trade-offs limiting SRAM scaling

This research will also explore alternative devices and materials tailored for low-leakage, SRAM-specific processes to understand the fundamental limits of leakage in ultra-large SRAM arrays. Additionally, techniques such as pattern-dependent read/write access and low-swing interconnects will be investigated to reduce dynamic energy consumption.

Backside technology will be leveraged for circuit assist features, providing new opportunities for power delivery and performance enhancements.

Complete SRAM memory circuits will be designed using imec’s predictive PDK for the A14 node and beyond, enabling comprehensive PPA benchmarking. Selected circuit and technology innovations will be taped out and fabricated through industry collaboration and/or imec’s internal fabrication platforms.