DRAM (or dynamic random access memory) is predominantly used as the computer’s main memory – the memory from which the central processing unit (or CPU) reads its instructions. Through the years, different DRAM standards have emerged, serving different needs and applications. Each standard has been further developed into different generations in order to answer the need for ever increasing bandwidth. In this article, Timon Evenblij, system memory architect at imec, and Gouri Sankar Kar, program director at imec, review different DRAM flavors and identify common trends and bottlenecks. They also propose the routes that imec follows in order to push DRAM performance to its ultimate limits.
DRAM: the basics
Before diving into different DRAM flavors, let’s start with the basics – based on a lecture from prof. O. Mutlu.
Any memory is built up using bit cells, which is the semiconductor structure that stores exactly 1 bit, hence its name. For DRAM memories, the bit cell consists of a capacitor and a transistor. The capacitor is used to store a charge, and the transistor is used to access the capacitor, either to read how much charge is stored or to store a new charge. The wordline is always connected to the transistor gate, controlling the access to the capacitor. The bitline is connected to the source of the transistor, reading the charge stored in the cell or providing the voltage when writing a new value to the cell. This basic structure is very simple and small, so manufacturers can process a very large amount of them on a die. One disadvantage is that the single transistor is not very good at keeping the charge in the small capacitor. It will leak current from or to the capacitor, making it lose its well-defined charge state over time. This problem is circumvented by periodically refreshing DRAM memories, which means reading the content of the memory and writing it back. Attentive readers might have noticed that when a charge is read from the capacitor, it is gone. After reading a value from a DRAM cell, the value should be written again. This is what gives the name ‘dynamic’ to DRAM.