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How to efficiently cool power electronics and optoelectronic sensors?

The downside of an ever-increasing chip density is a dramatic increase in the system’s heat generation. This is for example true for smart factory and smart mobility applications, that implement the latest generation of power electronics components. Philippe Soussan, program director within the sense & actuate unit of imec, and his team present a cooling solution that uses optimized Si-based microchannel structures, capable of removing large amounts of excess heat. On top of that, the solution can easily be tuned towards other applications. 

Heat generation – the downside of increasing chip density

Bringing more and more miniaturized and high-performance components together in increasingly smaller packages is a major trend in the manufacturing of electronic products. This evolution is well-known in the microelectronics industry, where 3D integration technologies are increasingly used to generate compact high-performance computing systems, as one way to further extend Moore’s Law. The trend is also emerging in a variety of related application domains that are more driven by system constraints, including, for example, the smart factory and smart mobility. Here, smart robot solutions – self-guided by sensors and actuators – are equipped with compact high-performance microsystems. These systems typically implement the latest generation of power electronics, able to work at high frequencies and to withstand high temperatures.

But the downside of this evolution is a dramatic increase in the system’s heat generation – negatively impacting its performance and reliability.

Today’s air-cooling solutions are inadequate to remove the excess heat in small form factors. This situation calls for innovative technologies able to remove the large amounts of heat from the small system area.

With respect to smart factory robots or autonomous vehicles, the requirements for heat removal from, for example, power devices are challenging to meet. Heat sinks must be robust, low cost and have a high cooling performance – capable of reaching heat dissipation levels of 500W/cm2 and beyond. In case a liquid is used for heat removal, no leakage of the liquid towards the system can be tolerated. Moreover, the space for implementing any liquid-containing cooling system is very limited, and the cooling system may not limit the robot’s mobility. 

Why choose a microfluidics heat sink?

Through the years, a variety of cooling solutions, including air-cooled heat sinks, two-phase refrigeration and jet impingement systems, have been explored – all coming with their own advantages and drawbacks. Among the various approaches, the use of microchannel structures turned out to be very effective as heat sinks. These microchannels serve as flow passages for a cooling liquid (such as water), which in general is more effective in removing heat compared to air. This greater effectiveness is due to the liquid’s higher thermal conductivity and specific heat capacity. By pumping the liquid into small, parallel, high-aspect-ratio microchannel structures, the convective heat transfer surface area and the heat transfer coefficient is further increased, enabling a high heat flux removal.

Microchannel arrays have already been extensively studied since their first introduction in the early 1980s. Although using microchannels to cool electronics is attractive, their use and cost-effective implementation remained challenging until now.

The cost issue can be resolved by using silicon (Si)-based fabrication processes – with Si being a high thermal conductive solid. Si-based technology allows the fabrication of high-quality and low-cost devices, with a high yield and large volume, by leveraging massively parallel production processes.

In order to increase the heat transfer performance of the microchannels, varying channel dimensions and structures in different configurations have been explored. In many cases, a tradeoff had to be made between a decreasing overall thermal resistance and an increasing pressure drop along the channels – which is known to negatively affect the heat transfer performance.  

Imec’s approach: tuning the channel dimensions 

A team of researchers at imec has developed a Si-based microchannel heat sink that can be fabricated separately and then interfaced to the backside of a target heat-dissipating chip.

The team’s major objective was to minimize the system’s total thermal resistance by optimizing the heat sink’s channel width and height for a given flow rate and pressure drop, and by finding an optimized process for bonding the two chips.

Optimized dimensions for continuous straight channels were obtained from both analytical and numerical calculations, and validated experimentally. Following the analytical study, the total thermal resistance can be described as the sum of the conduction resistance, the convective resistance, the caloric resistance and the contact resistance. The convective resistance, which accounts for the ability to transfer the heat from the solid heat sink surfaces to the liquid, largely depends on the channel dimensions. The contact resistance accounts for the interface thermal resistance between the two Si pieces and can be minimized by optimizing the bonding process.

Once the optimized microchannel geometry and bonding parameters are found for a given flow and pressure drop, 3D thermal and fluidic simulations are performed to predict the fluidic performance and thermal behavior of the heat sink. 

By using the approach described above, the design and fabrication of the microfluidic heat sink can be tailored to any external system constraints, such as space or liquid supply.

Key ingredient: high-aspect ratio microstructures 

The above approach was applied for developing an optimized Si-based microfluidic heat sink assuming a maximal water flow rate of 150mL/min and a maximal pressure drop of 2.5bar. 

Figure 1: Schematic view of the micro-cooler.

Schematic view of the micro-cooler.

Analytical calculations revealed an optimal channel width of about 20-30µm for a channel height between 150 and 250µm. Based on these results, microstructures with 30µm channel width and target channel depth of 250µm were designed.

Figure 2: Analytical calculation of the total thermal resistance considering different channel dimensions, assuming a flow rate of 150mL/min and a maximal pressure drop of 2.5bar.

Analytical calculation of the total thermal resistance considering different channel dimensions, assuming a flow rate of 150mL/min and a maximal pressure drop of 2.5bar.

Microchannel heat sinks with these dimensions were subsequently fabricated using advanced CMOS-compatible Si fabrication processes. In particular, the deep reactive-ion etch (DRIE) process was used to fabricate microchannels with a challenging high aspect ratio – key components of the micro-cooler.

Figure 3: Scanning electron micrograph (SEM) of the high-aspect ratio microchannels.

Scanning electron micrograph (SEM) of the high-aspect ratio microchannels.

The heat sink can be interfaced to the backside of any heat-dissipating chip using fusion bonding and thermocompression bonding. In this study, a 5x5mm2 thermal test chip that was able to generate a high heat flux and to sense the temperature variation via tungsten (W) resistors was used. By using an optimized copper/tin-gold (Cu/Sn-Au) interface, a very low thermal contact resistance was achieved between both parts. 

Figure 4 – Photograph of imec’s Si-based microfluidic heat sink.

Photograph of imec’s Si-based microfluidic heat sink.

Robust, fully sealed channels were obtained in a so-called ‘closed channel’ configuration. The team also studied an alternative configuration, called ‘open channel’. In this configuration, an even lower thermal resistance can be expected. But the sealing of the channels entirely relies on the bonding process between the two Si pieces – which is a more challenging approach. Alternatively, the channel wafer can be directly bonded at full wafer scale for even less thermal resistance.

Cooling results: a power dissipation of 600W/cm2 (and beyond)

Imec’s compact heat sink assembled to the thermal test chip achieves a total thermal resistance as low as 0.34K/W at less than 2W pump power. 

It enables a high heat flux removal far beyond any conventional air based heatsink. This makes it possible to dissipate power of more than 600W/cm2 while keeping the component temperature below 100°C.

The cooling chip typically contains 67 parallel channels, implemented in a small form factor of the order of a few tens of mm2

Cooling the next generation of applications

The cooling performance of the cooling chip and the tailored approach to the chip design make the proposed solution particularly appealing for any application that is dealing with high-performance thermal management of wide-bandgap optoelectronics materials, and with the cooling of read and drive circuitry. 

This covers in a non-exhaustive way the following applications:

  • Radio-frequency/microwave modules for the next generation of telecom systems with high-performance directive antennas. Such modules typically rely on the integration of a heat generating power amplifier to be able to deliver a strong burst to the antennas. Current solutions remain very bulky.
  • Next generation of power electronics modules based on GaN or Si. These are typically used for engine, drive train and electric motor management of cars, robots and in the uprising generation of electric vehicles.
  • Novel integrated sensors for light detection and ranging (LiDAR), spectrometry relying on the III-V integration with CMOS and photonics technologies. Current systems that are based on free space optics are not scalable by nature. An effective cooling solution will be needed especially for the laser integration.
  • Temperature management of specialty microelectromechanical systems (MEMS) products for lab-on-chip applications. These systems typically have a drive and read IC connected to a MEMS (fluidic) device. Such micro-systems are getting vastly adopted in the biomedical field where the chip temperature needs to remain cold in order to avoid destroying a large variety of (bio)chemical agents. 

Summary

Imec has proposed a miniature Si-based microfluidics heat sink demonstrating thermal power dissipation of over 600W/cm2. The thermal performance of the fabricated devices compares favorably to microelectronics coolers presented in literature. At the heart of the device are small, parallel high-aspect-ratio microchannel structures, fabricated with CMOS-compatible fabrication processes, thereby ensuring low-cost final devices. An important asset of the proposed solution is the ability to accurately predict and optimize the fluidic performance and thermal behavior prior to chip design and fabrication. This allows the solution to be easily tuned according to the requirements and restrictions imposed by the application, in terms of, for example, available space or liquid supply. 

The new cooling approach can potentially meet the heat challenge that faces the new generation of power electronics, sensors and high-performing devices in a variety of systems. The proposed solution is expected to enable applications beyond the microelectronics industry.

This article was first published in Chip Scale Review (Sept. – Oct. 2019). 

Want to know more?

  • More details of this study can be found in the paper ‘High performance thermal management using miniature low cost microfluidics heat sink’, by P. Soussan et al, presented at the 2019 Embedded World Conference. This paper can be requested via our contact form.
  • Imec also develops cooling solutions for high-performance chips, e.g. for datacenter applications. Read the article in imec magazine.

About Philippe Soussan

Philippe Soussan is currently program director within the sense & actuate unit of imec. His field of expertise covers the interaction between processes and material properties, as well as wafer scale technology integration in the field of multi-physics devices. This comprises 3D interconnects, micro-fluidics and lately integrated photonics. Philippe has authored or coauthored more than 130 publications and owns more than 15 patents.

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