Background calibration for emerging time-interleaved ADC architectures

Popular cloud-based applications such as video-on-demand, internet search engines, streaming, and social media rely all on warehouse-scale data centers, which comprise tens of thousands of computing nodes interconnected via high-capacity optical links, from server-to-server connections up till extended ranges within metro and regional networks. Optical transceivers for these links currently feature data rates in the 100Gb/s to 400Gb/s range, which are achieved by parallelizing several lanes, e.g. 4 lanes of PAM-4-modulated data at >50Gbaud (100Gb/s) per lane. Emerging standards like IEEE 802.3dj and OIF CEI-224G target transmission speeds for 800Gb/s and even 1.6Tb/s with increased lane data rates of 100Gbaud and beyond.

A critical component in state-of-the-art optical transceivers is an analog-to-digital converter (ADC) with moderate resolution and very high sampling rate (>>100GS/s). Such ADC allows the implementation of advanced digital signaling processing (DSP) algorithms for equalization, detection and error correction, which are required to recover the transmitted data from signals that are heavily distorted due to various impairments, including limited bandwidth of front-end electronics, optical modulators and detectors; chromatic dispersion in the optical channel, etc. The ADCs in these systems typically require bandwidths of more than the lane baud rate, resulting in bandwidth specifications of >>100GHz.

CMOS scaling in deep-nanoscale nodes has enabled designing ADCs with very high sampling rates by time-interleaving (TI) several lower-speed channels. Small differences between the channels pose limitations on the maximum achievable signal quality after conversion, in the form of a degraded effective number of bits and spurious tones in the signal spectrum. Calibrating these errors restores the performance. Such calibration algorithms preferably runs in the background to allow uninterrupted operation of the ADC. For errors that are also dominant in TI ADCs at low sampling speeds (e.g., gain and offset differences), various solutions have already been developed. New errors rise in ultra high-speed ADCs due to errors in the transfer functions of the different channels leading to, e.g., bandwidth and settling time errors. Also errors like misalignment of different clock signals become more severe. Furthermore, emerging high-speed ADC architectures like time-based ADCs and TI slope ADCs lead to efficient A/D conversion but they also introduce new errors due to, for instance, nonlinearities in conversion between voltage- and time-domain signals, or by imperfect shape of the slope signal. For these new and extra errors, no general solutions for background calibration have been developed yet, limiting the maximum performance that can be achieved.

The goal of this PhD is to investigate and implement techniques for the realization of background calibration for moderate-resolution ADCs with sampling rates well in excess of 100GS/s. In a first phase, algorithms will be developed using a high-level model of the ADC and critical blocks for the calibration will be identified. The second step of the PhD consists in an actual circuit- and layout-level implementation of such ADC including the critical circuits needed to run the calibration. In a final step, such chip will then be characterized to verify the proposed techniques using the high-speed measurement infrastructure available at imec.

This PhD takes place in the imec team of Jan Craninckx and Piet Wambacq, one of the world-leading groups in the areas of high-performance RF, millimeter-wave, and ADC design, with a strong publication record in the major conferences and journals of the solid-state circuits community. This is a challenging PhD topic, requiring a highly motivated PhD student with strong interest in developing design skills in advanced CMOS nodes.