Design and Integration of RF/Mixed-Signal Interposers for High-Bandwidth Wireline Applications in Co-Packaged Optical Systems

Motivation and Background

The exponential growth of bandwidth demand in emerging applications such as artificial intelligence (AI) training, inference, and cloud computing is pushing traditional electrical interconnects to their physical and power-efficiency limits. At very high data rates, conventional pluggable optics struggle with increasing power consumption, degraded signal integrity, and limited form factor scalability.

Co-packaged optics (CPO), which integrate optical transceivers onto the same substrate (or eventually interposer) as the ASIC, provide a promising solution by significantly reducing electrical interconnect length to the optics, thereby minimizing insertion losses and lowering system power consumption. However, this paradigm introduces complex design challenges, requiring holistic co-design across electronics, photonics, and packaging domains.

Problem Statement

The realization of next-generation co-packaged optical transceivers requires simultaneous support for ultra-high data throughput and low-loss RF signal routing on a unified platform. Key challenges include:

• Heterogeneous integration platforms that enable high-density, low-loss interconnects between electronic ICs (EICs) and photonic ICs (PICs) while preserving bandwidth scalability.
• Wireline architectures optimized for high-speed digital I/O, demanding low crosstalk, high bandwidth density (high Terabit/s/mm), and energy-efficient operation (low pJ/bit).
• RF/mixed-signal driver EICs capable of efficient interfacing between the ASIC and the optics.

Current solutions either escalate system cost, introduce insertion loss and crosstalk, or fail to achieve the required balance between performance, scalability, and manufacturability. A co-optimized heterogeneous integration framework is therefore essential to meet the demands of next-generation optical interconnects.

Research Objectives

This PhD will pursue the following objectives:

• Optimize Imec RF/mixed-signal interposers enabling high-density, low-loss electrical links design among ASICs, driver ICs, and PICs.
• Design high-Q passive components (capacitors, resistors, inductors and matching networks) within IMEC RF/Mixed-Signal interposers to reduce active chip area and system cost.
• Investigate hybrid integration strategies that combine on-chip active circuits with interposer-embedded passive networks, enabling co-optimization for performance and manufacturability, and benchmark against alternative integration technologies.
• Design, simulate, and experimentally validate:
• High-speed, low-power SerDes with minimized jitter.
• Efficient EICs for optical modulation across different integration approaches.
• Interposers optimized for interconnect with low insertion loss, crosstalk, and parasitic.
• Fabrication of a demonstrator based on a co-simulation and co-optimization framework that integrates photonic and electronic subsystems with dense, low-parasitic interconnects, thereby enabling enhanced energy efficiency and scalable data rates.

Methodology

• Modeling and simulation: Multi-domain co-simulation of SerDes, RF drivers, photonic modulators, and interposer structures.
• Co-design of EICs and RF/mixed-signal interposers with embedded passive components and optimized high-frequency routing.
• Prototype fabrication: Fabrication of test structures and integrated demonstrators on imec’s RF/mixed-signal interposer platform.
• Experimental characterization: S-parameter measurements, eye-diagram analysis, and system-level validation of energy efficiency and data rate.

Expected Outcomes

• Demonstration of low-power, high-speed SerDes interfaces optimized for co-packaged optics (CPO).
• RF/mixed-signal interposer demonstrators with minimized parasitics, insertion loss, and crosstalk.
• A unified co-simulation and co-optimization framework integrating EIC, PIC, and packaging design considerations.
• Experimental proof-of-concept of a heterogeneous, co-packaged optical transceiver achieving good energy efficiency and bandwidth scalability relative to current state-of-the-art solutions.