High-Level Physical-Aware System Simulation of Machine Learning Accelerator Models

Deep learning accelerators are an integral part of most modern compute system architectures. This work involves performance and power modeling of such a system in a full-system context via virtual platform modeling & simulation. This enables early design space exploration of the system at the early stage of full system design based on the PPA metrics. Performance modeling at the system level would be a very important part of this procedure. The goal of this project is to enable integrating Machine Learning (ML) accelerator in a virtual platform. In the first phase of this project, the accelerator RTL model will be integrated in the simulation framework, and various ML applications will be validated within the full system. In the second phase of this project a transaction-level model (SystemC/TLM) of the accelerator will be replaced with the RTL model to provide faster system evaluation and finding the capabilities of fast modeling. The last phase will be integrating the accelerator power model in parallel with the TLM model to have fast power estimation at the system-level.

Objectives:

• Integrating an ML accelerator in a virtual platform
• Validating the model using ML applications
• Hardware / Software partitioning of ML workloads
• Power modeling and analysis at high-level simulation framework

Skills:

• Strong programming skills C++ 
• Good understanding of hardware design and Register transfer level design (RTL)
• Good understanding of computer architectures and memory hierarchy  
• Experience with ML workloads and machine learning concepts
• Familiarity with SystemC/TLM or any simulation frameworks is a plus (e.g., Gem5, ..)