Nanoscale electrochemistry of materials and devices for next-generation semiconductor technology

Over the past decades, the semiconductor industry managed to continuously increase performance at an impressive, steady rate by scaling down the dimensions of all parts of the integrated devices (e.g. transistors and memory arrays) to dimensions of just a few nanometres. To further continue this trend and/or enable novel technologies, a deeper understanding of the impact of material surfaces and interfaces on device functionality needs to be developed.

Specifically, many questions regarding the (electro)chemical properties of interfaces at the nanometre scale remain. One of the reasons is the lack of metrology that can both characterize and control surface properties. An experimental method which allows for such a localized investigation is Scanning Electrochemical Cell Microscopy (SECCM). A schematic of the setup is shown in Figure 1. For a typical experiment, a liquid droplet (diameter a few tens of nanometres) is accurately positioned (piezo-controlled stage) on experimental chips that are designed to contain all relevant materials and have device dimensions that will be used in future chips that the industry needs to manufacture.

At the start of the project, research will be performed using nanopatterned electrodes (cylindrical holes (diameter 80 nm, depth 1 micron) in a dielectric matrix) that are to be filled by electrodeposited metal(s) (e.g. Cu, Ni, Co). By modulating the metal thickness of individual layers (thickness of a few nm), it is possible to ‘write’ information. For ‘reading’ the information that is stored in the metal multilayered stack, the latter is electrochemically dissolved in a controlled way, and the modulated signal (dissolution potential) is monitored, characterizing such a memory concept, which has been shown by Université Libre de Bruxelles (ULB) and imec during initial explorations with this approach. However, many factors (e.g. nanopattern ‘wetting’ by the liquid, deposition (‘writing’) and dissolution (‘reading’) current/potential waveforms, variability in the ‘write’ and ‘read’ steps, data retention time, the impact of solution composition, ...) need to be systematically studied and understood to further improve the stability. Additionally, for next-node interconnects it is foreseen that similar structures will be one of the crucial building blocks for making ever higher performing chips. Therefore, the test patterns will also be used to develop a better understanding of electrodeposition in high-aspect ratio, nanometre wide structures, which are increasingly important in semiconductor manufacturing. 

To further complement the learning, local electrochemistry studies of surface passivation, corrosion, and the effect of corrosion inhibitors will serve to develop higher performant wet-chemical etching and Chemical Mechanical Planarization (CMP) processes (Figure 2). During silicon wafer processing, both process steps are used tens of times, therefore, nanoscale insights and control of both the desired (wet etching) and undesired (corrosion) metal dissolution is critical. As SECCM enables one to define the electrochemistry in a precise way and enable high-throughput local surface chemistry modifications at pre-defined locations and in a wide range of patterns (see Figure 1 and 2), both material deposition and etching will be explored.

In the project, the PhD student will perform experimental work using a SECCM setup and develop a detailed understanding of (electro)chemical properties of surfaces, interfaces, and combinations of materials. Research will be performed both at ULB and imec, which will ensure that state-of-the-art nanopatterned structures can be produced. The PhD candidate will work in a challenging, highly dynamic, multicultural environment and the industry-relevant work will help in designing new chips for a range of applications.