/Nanoscale electrochemistry of materials and devices for next-generation semiconductor technology

Nanoscale electrochemistry of materials and devices for next-generation semiconductor technology

PhD - Leuven | Just now

Understanding deposition, etching, and corrosion at the nanoscale to enable novel chip technologies
Over the past decades, the semiconductor industry managed to continuously increase performance at an impressive, steady rate by scaling down the dimensions of all parts of the integrated devices (e.g. transistors and memory arrays) to dimensions of just a few nanometres. To further continue this trend and/or enable novel technologies, a deeper understanding of the impact of material surfaces and interfaces on device functionality needs to be developed.

Specifically, many questions regarding the electrochemical properties of interfaces at the nanometre scale remain. One of the reasons is the lack of metrology that can both characterize and control surface properties. An experimental method which allows for such a localized investigation is Scanning Electrochemical Cell Microscopy (SECCM). A schematic of the setup is shown in Figure 1. For a typical experiment, a liquid droplet (diameter a few tens of nanometres) is accurately positioned (piezo-controlled stage) on experimental chips that will be designed to contain all relevant materials and have device dimensions that will be used in future chips that the industry needs to manufacture.

At the start of the project, research will be performed on an imec-developed memory technology (‘Electrolithic Memory’), in which nanocylinders (typical diameter 80 nm and depth 1 micron) are filled by electrodeposited metal multilayers (e.g. Cu and Ni). By modulating the metal thickness of the individual layers (thickness of a few nm), it is possible to ‘write’ information. For ‘reading’ the information that is stored in the metal multilayered stack, the latter is electrochemically dissolved in a controlled way and the modulated signal (dissolution potential) is monitored, allowing one to retrieve the stored data. The proof-of-concept of using SECCM for this novel memory has been shown by Université Libre de Bruxelles (ULB) and imec. However, many factors (e.g. nanopattern ‘wetting’ by the liquid, deposition (‘writing’) and dissolution (‘reading’) current/potential waveforms, variability in the ‘write’ and ‘read’ steps, data retention time, the impact of solution composition, ...) need to be systematically studied and understood to further improve the stability, quality, and data density of the memory chip. Primarily, the experimental work serves as input for the design of peripheral electronics that will be crucial for the industry to adopt this novel memory concept for long-term information storage in data centres. Secondarily, the work will result in a better understanding of electrodeposition and -dissolution in high-aspect ratio, nanometre wide structures, which are increasingly important in semiconductor manufacturing.

To further complement the learning on electrodeposition and -dissolution, local electrochemistry studies of surface passivation, corrosion, and the effect of corrosion inhibitors will serve to develop higher performant wet-chemical etching and Chemical Mechanical Planarization (CMP) processes (Figure 2). During silicon wafer processing, both process steps are used tens of times, therefore, nanoscale insights and control of both the desired (wet etching) and undesired (corrosion) metal dissolution is critical. As SECCM enables one to define the electrochemistry in a precise way and enable high-throughput local surface chemistry modifications at pre-defined locations and in a wide range of patterns (see Figure 1 and 2), both material deposition and etching will be explored.

In the project, the PhD student will perform experimental work using a SECCM setup and develop a detailed understanding of (electro)chemical properties of surfaces, interfaces, and combinations of materials. Research will be performed both at ULB and imec, which will ensure that state-of-the-art nanopatterned structures can be produced. The PhD candidate will work in a challenging, highly dynamic, multicultural environment and the industry-relevant work will help in designing new chips for a range of applications.


Required background: Chemistry, Materials Science

Type of work: 80% experimental, 10% characterization, 10% literature

Supervisor: Jon Ustarroz

Co-supervisor: Harold Philipsen

Daily advisor: Senne Fransen

The reference code for this position is 2026-154. Mention this reference code on your application form.

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