/Thermal Gradients Induced Reliability Challenges in Advanced Interconnects

Thermal Gradients Induced Reliability Challenges in Advanced Interconnects

PhD - Leuven | Just now

Redefining chip reliability under the unseen force of thermal gradients.
Recent developments in nanoelectronics chips, especially in advanced metal nano-Through Si Vias (nano-TSVs) and metal interconnects used for back-side power delivery (BSPDN), have resulted in significant thermal gradients during both chip operation and reliability testing. Similarly, in silicon photonics, metal interconnects used in these applications require high current densities, which also generate thermal gradients. These gradients are the driving force for thermomigration (TM) and increasingly threaten metal interconnect reliability alongside electromigration (EM) and stress migration (SM).

 

Previous studies on TM in metal interconnects have primarily focused on sub-micron Cu lines, using on-chip heaters to impose thermal gradients. Lifetime models have been developed and validated for such Cu-based structures. However, these models still need to be confirmed for alternative metallization schemes such as Co and Ru, as well as across scaled line dimensions. The scaling behavior of the underlying physical mechanisms remains unclear, yet it is critical for advanced technology design. Moreover, the broader impact of thermal gradients from individual metal lines to the full-chip architecture remains largely unexplored, and transferring reliability insights into advanced interconnect platforms remains necessary.


The goal of this PhD project is to investigate the reliability of advanced interconnects under thermal gradients. The research aims to achieve the following outcomes:

  • Gain a deeper understanding of the TM failure mechanism and its interplay with EM in metal line structures.
  • Investigate TM‑induced void dynamics and their interaction with EM and SM.
  • Characterize the impact of thermal gradients on the metal line lifetimes across scaled line dimensions (90 nm to 20 nm) and metallization schemes, including Cu, Co BEOL, nano-TSVs, and BSPDN.
  • Develop a TM+EM-aware lifetime prediction framework applicable to realistic chip environments.

The proposed research activities include:

  • Developing a strong physical understanding of SM, EM, and TM.
  • Performing in-situ measurements with nanoprobing techniques in SEM to monitor degradation caused by SM, EM, and TM in available samples.
  • Conducting reliability characterization of advanced metal line structures through electrical measurements and failure analysis to identify failure modes and their locations.
  • Designing dedicated test structures using commercially available technologies, supported by accurate thermal analysis with finite element modeling.
  • Developing a lifetime prediction model by integrating experimental data with established reliability models, in collaboration with the thermal management team.



Required background: Master’s degree in Electrical Engineering, Materials Science, Physics, or a related field.

Type of work: Literature (10%). Modeling (30%), Test structure design (10%), Experimental (50%)

Supervisor: Kristof Croes

Daily advisor: Youqi Ding, Olalla Varela Pedreira

The reference code for this position is 2026-173. Mention this reference code on your application form.

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