To Stories
Imec Achieves Record-Low Source/Drain Contact Resistivity for PMOS Transistors
Share this article on
Reading room
Silicon photonics technology for next-generation datacenter interconnects
How to efficiently cool power electronics and optoelectronic sensors?
Make smartphones and autonomous vehicles see the impossible
Solving the contact resistance challenge for 7nm and beyond CMOS
A cold shower for chips
Sensor searches demanding application
A 300mm platform for 2D-material based MOSFET devices
Iuliana Radu on quantum computers
Press
Imec improves performance and understanding of stacked nanowire Gate-All-Around transistors for N3 and beyond
Press
Imec and partners report major breakthroughs for spintronic logic devices in two different implementations
Press
Imec demonstrates the feasibility of introducing SST-MRAM as a last-level cache at the 5nm technology node
Press
Imec first to stack FinFETS with 45nm fin pitch using sequential 3D integration
Published on:
8 June 2017
Share this article on
Contact us
