The search for novel ways to treat cognitive, sensory, and motor disorders, and their associated impairments – from restoring movement in people with paralysis, and enabling intuitive control of prosthetic limbs, to re-establishing speech and vision – is in full swing. In parallel, neuroscience is pushing for more powerful tools to probe neural dynamics and unravel the mechanisms underlying cognition. These advances are increasingly driven by brain-computer interfaces (BCIs), which directly connect the brain to electronic systems and hold enormous promise for both transformative therapies and deeper scientific insight.
Cortical BCIs – systems that record electrical activity from the cortex – come in a variety of flavors. Intracortical BCIs (iBCIs), for instance, employ microelectrode arrays (MEAs) implanted within the cerebral cortex, while electrocorticography (ECoG)-based systems place electrodes on the cortical surface, between the skull and the brain tissue. Despite their differences, both aim to capture fine-grained electrical activity from large populations of neurons. But as the number of underlying recording channels increases, so does the volume of neural data that must be transmitted and processed.
The challenge: this data surge drives up power consumption and, consequently, heat generation – while even small temperature increases can irreversibly damage neurons. As a result, lossless data reduction and compression become essential, cutting the number of transmitted bits without compromising the fidelity of the underlying neural information.
Why ‘simply’ increasing (MEA) recording channels and (wireless) bandwidth is not enough
Scaling BCIs is a deeply complex, system‑level challenge. Let’s take iBCIs as an example. First, at the recording front-end, MEA neural probes must continue to grow in channel count to eventually reach several thousand parallel electrodes – well beyond the 1,536 channels offered by today’s (state-of-the-art) Neuropixels 2.0 Quad Base (QB).
At the opposite end of the system, (i)BCIs must sustain high-bandwidth, low-latency communication with (external) decoding and processing hubs. Here, impulse-radio ultra-wideband (IR-UWB) has emerged as a promising technology. Beyond eliminating the usability and comfort constraints of wired links, IR-UWB combines electromagnetic regulatory compliance with data rates above 124Mbps over distances of tens to hundreds of centimeters, low power (roughly 30mW, which is around 10x lower than Wi-Fi), strong interference resilience, and inherent physical-layer security.
Still, even the most advanced UWB links cannot meet the bandwidth requirements imposed by future, high-density MEAs. Streaming raw data from an existing 1,500-channel probe such as the Neuropixels 2.0 QB demands throughputs well over 500Mbps, far beyond UWB’s practical operating range. Pushing toward 10,000+ parallel channels only widens this gap.
These bottlenecks shift the pressure onto the on-chip compression technology that bridges the MEAs (or any other recording devices) and the wireless interface. Concretely, it will need to incorporate advanced, lossless data reduction to dramatically shrink data volume while preserving the full dynamic range and information content of the recorded signals. Unfortunately, conventional strategies rely on large memory buffers, heavy digital logic, or lossy approximations – rendering them unsuitable for use in heavily constrained (i)BCIs.
A neuromorphic compressive telemetry (NCT) chip for lossless data reduction
To meet the data-rate, power, and thermal constraints of next-generation (intracortical) BCIs, imec has developed a new neuromorphic compressive telemetry (NCT) chip for lossless, realtime data reduction. The architecture is built around two key innovations (Y. He et al., 2024), (P. Russo et al., 2026):
- Send-on-delta signal acquisition, replacing traditional Nyquest-rate sampling with an event‑driven scheme that produces data only when the neural signal changes.
- A ternary packet-based AER serializer (eSER), which groups these events into compact packets for efficient serialization and deterministic transmission.
Together, these building blocks allow the NCT to eliminate redundant data – thus lowering (i)BCIs’ power and bandwidth requirements, while preserving all the information needed for high-fidelity spike reconstruction.

Figure 1: Imec has developed a neuromorphic compressive telemetry (NCT) chip for lossless, realtime data reduction. Source: imec.
Send-on-delta encoding for lossless, event-driven signal acquisition
Most cortical neurons fire surprisingly infrequently – typically less than ten hertz, meaning just a few dozen spikes per second (and often even less). This inherent sparsity presents a major opportunity for data compression and reduction.
Traditional Nyquist-rate sampling captures signals at a fixed frequency – commonly 20-30kHz for neural sensing – regardless of whether any neural event (i.e., spike) is actually occurring. This produces a continuous stream of samples, the vast majority of which are redundant (when neurons are silent).
Imec’s send-on-delta sampling/encoding approach takes a fundamentally different path. Instead of sampling at fixed intervals, send-on-delta proposes an event-based, signal-dependent temporal sampling scheme: data is generated only when a signal changes by more than a predefined threshold (Δ). Thus, the output is not a dense waveform, but a sparse stream of information-rich events.
This brings several advantages: drastically fewer data points (often by an order of magnitude), significantly lower power consumption, and much lower bandwidth needs – while all spikes are captured with high fidelity.
A key improvement in imec’s latest (second-generation) send-on-delta mechanism is that the encoding now operates fully in the digital domain: instead of starting from raw analog voltages passing through a power-hungry send-on-delta analog-to-digital converter (ADC), the system works with a digital-state representation that reflects meaningful changes in the neural signal. In simple terms, send-on-delta digitally detects when the signal changes, and then decides what to do with the underlying data.
A ternary packet-based AER protocol for advanced packetization and serialization
While imec’s send-on-delta approach effectively exploits the sparsity of neural activity, it naturally produces spike-driven data streams (only when neural signals change, not at fixed intervals). This is desirable to achieve power savings, but it requires a communication method that can handle irregular, spike-driven data.
Address-event representation (AER) protocols are a common solution for spike-driven event communication. However, existing AER schemes show several limitations when applied to high-density neural recordings. For example, when multiple readout channels generate events at the same time, classical AER relies on event arbitration or acknowledgement-based handshaking – which does not scale well to large channel counts, and introduces unpredictable latency. In addition, neural spikes exhibit strong spatial correlation – a single spike may appear across several adjacent electrodes – yet traditional AER methods packetize and serialize each event independently, repeatedly transmitting redundant address information and incurring unnecessary protocol overhead.
To overcome these limitations, imec developed an event-based serializer (eSER) that combines send-on-delta with a ternary packet-based AER protocol – purpose-built for neural telemetry. Imec’s design introduces several key advantages:
- Event-driven serial transmission – only when neural activity occurs,
- Spatial grouping of correlated events – sending one compact packet instead of many little messages, which eliminates redundant metadata, and reduces protocol overhead by up to a factor of two,
- No need for arbitration or collision-handling logic – rather than arbitrating between simultaneous events, the eSER first collects all Δ outputs and then emits one packet in a controlled sequence; this completely avoids event collisions, while removing the need for complex arbitration circuitry with indeterministic latency – a major bottleneck in conventional AER,
- Rich, multi-bit (ternary) encoding for lossless reconstruction – imec’s AER packets contain Δ values, direction of change, and the channel ID to enable lossless spike waveform reconstruction (even for low amplitude spikes down to ~31 µV).
As such, imec’s AER solves the scalability, complexity, overhead, (indeterministic) latency, and power concerns of traditional implementations by aligning communication with the true nature of neural signals – sparse, bursty, and spatially correlated. By intelligently grouping events, encoding richer Δ information, and activating the serializer only when needed (when Δ does not equal zero), the system filters out redundant data at the source and achieves dramatically higher compression and ultra-low power operation.

Figure 2: Imec’s approach combines send-on-delta encoding for lossless, event-driven signal acquisition with a ternary packet-based AER protocol for advanced packetization and serialization. Source: imec.
Validating imec’s high‑fidelity, low‑power telemetry using neural recordings
To evaluate its performance, imec tested its NCT chip – fabricated in 65nm CMOS – using in-vivo neural recordings from high-density datasets.
In these experiments, the system successfully digitized, compressed, packetized, serialized, and reconstructed neural activity from 384 recording channels in real time. Powered by imec’s send-on-delta approach and ternary packet-based AER scheme, the chip consistently achieved more than a ten-fold reduction in data volume, even after accounting for the packetization overhead.
Crucially, this level of compression was achieved without compromising spike fidelity. The system preserved spikes with amplitudes down to 31µV, reconstructing them with <23% normalized RMS error – equivalent to an SNDR of 12.7dB, which is well in line with the commonly-accepted threshold for reliable spike sorting. In other words, the compressed, serialized data stream retained all waveform features essential for downstream neural decoding (and analysis).

Figure 3: Imec’s NCT chip consistently achieved more than a ten-fold reduction in data volume, without compromising spike fidelity. Source: imec.
The complete NCT telemetry chain operates at exceptionally low power (consuming just 0.1µW per channel) and demonstrates record-breaking silicon efficiency, requiring only 27 bits of memory per channel – a 55-fold reduction compared to epoch-based compression schemes that rely on kilobits of buffer memory. This dramatically smaller memory footprint minimizes silicon area, lowers both leakage and dynamic power, and helps keep implant temperatures safely within clinical limits.
The importance of deterministic latency in distributed neural implants
Neural spikes are extremely brief – often well under 200µs in duration – with their precise timing carrying essential information about how the brain encodes movement, perception, and intent. In distributed (intra)cortical systems, where multiple recording channels record from different cortical regions at once, even small variations in transmission delay can distort the temporal relationships between spikes. To preserve these relationships, the telemetry system must maintain deterministic latency, with timing uncertainty kept to just a few microseconds.
Imec’s NCT architecture achieves this requirement by design. By eliminating arbitration delays, and avoiding global clock distribution, the system ensures that data from each sensor unit is aligned in real time. Measurements show a latency variation well below 10µs, comfortably meeting the microsecond-level precision needed for distributed spike-timing analysis. As recording channels scale and become increasingly spatially distributed, this deterministic timing ensures that neural activity can be reconstructed accurately across thousands of channels, without temporal drift or distortion.
Next step: scaling toward 10,000 channels
Imec’s most recent results show that its neuromorphic compressive telemetry architecture can already scale to 1,500 channels – on par with today’s highest-density MEA platforms – while delivering a 10x data reduction and maintaining high-fidelity spike reconstruction. This confirms that the core principles – i.e., the event-driven ‘send-on-delta’ signal acquisition, and ternary AER packetization/linearization – extend far beyond the initial 384-channel tests.
As a next step, the team is now complementing the NCT chip with an AI-enhanced auto-encoder to identify the ~1% of neural events that carry the most behavioral or clinical relevance. By selectively encoding and transmitting only this most informative subset, imec’s NCT architecture is projected to reach a 100x data reduction – unlocking practical scaling toward 10,000 recording channels.
Partner with imec
We invite electrophysiology data acquisition developers, BCI companies, and neurotech startups to collaborate – whether by integrating imec’s NCT chip into their platforms, or licensing the underlying IP blocks for (pre-clinical) research. Together, we can accelerate next-generation (i)BCIs and bring scalable, clinically-viable neural interfaces closer to reality.
Further reading:
Y. He et al., "An Event-Based Neural Compressive Telemetry With >11x Loss-Less Data Reduction for High-Bandwidth Intracortical Brain Computer Interfaces," in IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 5, pp. 1100-1111, Oct. 2024, doi: 10.1109/TBCAS.2024.3378973.
Pietro Russo et al., “Event-based SerDes Telemetry Network for Distributed Brain Computer Interfaces,” in 2026 Neuromorph. Comput. Eng. 6 014001, doi: 10.1088/2634-4386/ae2cc2
This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation program (grant agreement No. 101001448).
This article was previously published on EDN – at https://www.edn.com/neural-telemetry-new-chip-delivers-10x-compression-while-preserving-signal-integrity/

Yao-Hong Liu is currently Scientific Director at imec. He is a recipient of European Research Council (ERC) Consolidator grant. He is also a guest professor at Delft University of Technology. His current research focuses on wireless communication and edge computation for implantable brain-computer interfaces (BCIs) and IoT applications.Dr. Liu received his Ph.D. degree from National Taiwan University, Taiwan, in 2009. He was with Terax, Via Telecom (now Intel), and Mobile Devices, Taiwan, from 2002 to 2010, developing wireless transceiver ICs. Since 2010, he joined imec, the Netherlands, and is leading the research of the ultra-low power ASIC design. He received the IEEE Brain and Solid-State Circuits joint-society best paper award honorable mention 2022. He is currently a steering committee member of IEEE RFIC symposium.
Published on:
2 July 2026











