Introduction
The explosive growth of data traffic fuels the demand for ever more processing power and storage capacity. Moore’s Law continues to be necessary, but innovations are needed beyond this law to help managing the devices power, performance, area and cost. An Steegen reveals some of the secrets of semiconductor scaling – a pipeline full of materials, device architectures and advanced techniques that promise to further extend semiconductor scaling.
The end of happy scaling?
Data traffic explosion, fueled by the Internet of Things, social media and server applications, has created a continuous need for advanced semiconductor technologies. Servers, mobile devices, IoT devices... they drive the requirements for processing and storage. An Steegen: “At the same time, this trend is also creating more diversification. IoT devices for example will need low-power signal acquisition and processing, and embedded non-volatile memory technologies. For mobile and server applications, on the contrary, further dimensional scaling, continuous transistor architecture innovations and memory hierarchy diversification are among the key priorities.” But will we be able to continue traditional semiconductor scaling, as initiated by Gordon Moore more than 50 years ago? An Steegen: “For a long time, we have lived in the happy scaling era, where every technology node reshrinks and redoubles the number of transistors per area, for the same cost. But the last 10-12 years, we have not been following that happy scaling path. The number of transistors still doubles, but device scaling provides us with diminishing returns. We’ve seen these dark periods of ‘dark silicon’ before, but, fortunately, we’ve always managed to get out of these periods. Again, the technology box will provide new features to help manage power, performance and area node by node as we move to the next generation.”
The technology box for dimensional scaling
On the dimensional scaling side, extreme ultraviolet lithography (EUVL) is considered an important enabler for continuing Moore’s Law. An Steegen: “Ideally, we would need it at the 10nm node, where we will start replacing single exposures with multiple exposures. More realistically, it will hopefully be ready to lower the costs for the 7nm technology. At imec, we already showed that EUVL is capable of printing 7nm logic dimensions with one single exposure.” Still, issues need to be resolved, related to, for example, the line-edge roughness. An Steegen: “At the same time, to enhance dimensional scaling, we increasingly make use of scaling boosters, such as self-aligned gate contact or buried power rail. These tricks allow a standard cell height to be reduced from 9 to 6 tracks, leading to a bit density increase and large die cost reduction - a nice example of design-technology co-optimization.”
Improving power/performance in the front-end of line
FinFET technology has been the killer device for the 14 and 10nm technology nodes. But for the 7-5nm, An Steegen foresees challenges. “At these nodes, FinFET technology can’t meet the 20% performance scaling and 40% power gain anymore. To go beyond 7nm will require horizontal gate-all-around nanowires, which promise better electrostatic control. In such a configuration, the drive current per footprint can be maximized by vertically stacking multiple horizontal nanowires. In 2016, at IEDM, we demonstrated for the first time the CMOS integration of vertically stacked gate-all-around Si nanowire MOSFETs. Vertical nanowires, although requiring a more disruptive process flow, could be a next step. Or junction-less gate-all-around nanowire FET devices, which, as shown at the 2016 VLSI conference, appear as an attractive option for advanced logic, low-power circuits and analog/RF applications.” Further down the road, from the 2.5nm node onwards, fin/nanowire devices are expected to run out of steam. An Steegen: “Sooner or later, we will need to find the next switch. Promising approaches are tunnel-FETs, which can provide a 3x drive current improvement, and spin-wave majority gates.” Spin-wave majority gates with micro-sized dimensions have already been reported. But to be CMOS-competitive, they must be scaled and handle waves with nanometer-sized wavelengths. An Steegen: “In 2016, imec proposed a method to scale these spin-wave devices into nanometer dimensions, opening routes towards building spin-wave majority gates that promise to outperform CMOS-based logic technology in terms of power and area reduction.”
Extending or replacing Cu in the back-end-of-line
Looking ahead, it might as well be the interconnect that will threaten further device scaling. Therefore, the back-end-of-line (BEOL) and the struggle to keep scaling the BEOL needs attention as well. “We look at ways to extend the life of Cu, for example with liners of rubidium (Ru) or cobalt (Co). On the longer term, we will probably need alternative metals, such as Co for local interconnects or vias”, says An Steegen.
The future memory hierarchy
Besides a central processing unit, memory to store all the data and instructions is another key element of the classical Von Neumann computer architecture. The ever increasing performance of computation platforms and the consumer’s hunger for storing and exchanging ever more data drive the need to keep on scaling memory technologies. Besides this scaling trend, existing memories that make up today’s memory hierarchy are challenged with the need for new types of memory. An Steegen: “STT-MRAM, for example, is an emerging memory concept that has the potential to become the first embedded non-volatile memory technology on advanced logic nodes for advanced applications. It is also an attractive technology for future high-density stand-alone applications. It promises non-volatility, high-speed, low-voltage switching and nearly unlimited read/write endurance. But its scalability towards higher densities has always been challenging. Recently, we have been able to demonstrate a high-performance perpendicular magnetic tunnel junction device as small as 8nm, combined with a manufacturable solution for a highly scalable STT-MRAM array.” The future memory landscape also requires a new type of memory able to fill the gap between DRAM and solid-state memories: the storage class memory. This memory type should allow massive amounts of data to be accessed in very short latency. Imec is working there on MRAM and resistive RAM (RRAM) approaches.
Beyond classical scaling – towards system-technology co-optimization...
A challenge for traditional Von Neumann computing is to increase the data transfer bandwidth between the processing chip and the memory. And this is where 3D approaches enter the scene. An Steegen: “With advanced CMOS scaling, new opportunities for 3D chip integration arise. For example, it becomes possible to realize different partitions of a system-on-chip (SoC) circuit and heterogeneously stacking these partitions with high interconnect densities. At the smallest partitions, chips are no longer stacked as individual die, but as full wafers bonded together.” An increased bandwidth is also enabled by optical I/O. In this context, imec continues its efforts to realize building blocks (e.g. optical modulators, Ge photodetectors) with 50Gb/s channel data rate for its Si photonics platform.
Moore’s Law will continue, but not only through the conventional routes of scaling.
An Steegen: “We have moved from pure technology optimization (involving novel materials and device architectures) to design-technology co-optimization (e.g. the use of scaling boosters to reduce cell height). And we are already thinking ahead about a next phase, system-technology co-optimization. And to keep computing power improving, we are exploring ways beyond the classical Von Neumann model, such as neuromorphic computing, a brain-inspired computer concept, and quantum computing, which exploits the laws of quantum physics. There are plenty of creative ideas that will allow the industry to further extend semiconductor scaling...”
