Today’s back-end-of-line technology
Interconnects – the tiny wiring schemes in chips’ back-end-of-line – distribute clock and other signals, provide power and ground for various electronic system components, and interconnect the transistors within the chips’ front-end-of-line. Interconnects are organized in different metal layers, local (Mx), intermediate, semi-global and global wires. The total number of layers can be as many as 15, while the typical number of Mx layers ranges between 3 and 6. Each of these layers contains (unidirectional) metal lines (or tracks) and dielectric materials. They are interconnected vertically by means of via structures that are filled with metal. Since its introduction in the mid 1990’s, Cu dual damascene in combination with low-k dielectrics, has been the workhorse metal for lines and vias, in both logic and memory chip applications.
The traditional CMOS technology node scaling has required the dimensional reduction of the back-end-of-line structures, leading to reduced interconnect metal pitches. The most advanced technologies that are currently in production (i.e., the 10nm technology node) have M1 layers with metal pitches as tight as 36nm in order to fit with the scaling of the front-end-of-line (i.e., the transistors). While the dimensional scaling of FinFETs is expected to slow down, the back-end-of-line dimensions keep on scaling with ~0.7X to keep up with the required area scaling. At the same time, to maintain the back-end-of-line’s performance, the industry has started to embrace alternative types of metals (such as cobalt (Co)), and explore alternative low-k dielectric materials (such as air gaps).
The need for scaling boosters
But the downscaling of device dimensions below the 5nm technology node is becoming increasingly challenging. This is mainly due to electrostatic limitations in the front-end-of-line, and to routing congestion and a dramatic RC delay in the back-end-of-line. The RC delay results from a reduced cross-sectional area of the metal wires which drives up the resistance-capacitance product (RC) of the interconnect system. This, in turn, results in strongly increasing signal delay. These problems started a few nodes ago and are becoming worse with each technology generation.
One way to cope with these challenges is to introduce design-technology co-optimization (DTCO) complementary to the classical dimensional scaling. And this is where scaling boosters are coming in. Scaling boosters, such as self-aligned gate contact or buried power rail, enable a reduction of the number of tracks (or M2 pitch, as indicated in the figure below) thereby reducing cell height of a standard logic cell. And this will result in overall chip area reduction. Today’s mainstream technologies have standard cells with typically 7 to 12 tracks. Scaling boosters can bring this number down to 6, 5 or potentially even to 4.5 tracks. It has been demonstrated (using 5nm design rules) that scaling the track height from 6.5 to 4.5 tracks can produce an area gain of more than 30%.
Introducing the SuperVia
One of the newcomers in the scaling boosters family is a dual-damascene compatible SuperVia: a high-aspect-ratio via that provides direct connection from an Mx to an Mx+2 metal layer by bypassing an intermediate Mx+1 layer in a self-aligned manner. In a SuperVia, aspect ratios can reach 13 or higher. The SuperVia and the regular via can co-exist in the same design, with the SuperVia being implemented on those locations where there would be a benefit for ‘jumping faster’.
Benefits of the SuperVia: track height scaling and improved power distribution
The SuperVia could be an essential tool for scaling the number of metal tracks towards 4.5. In a 4.5-track cell with standard stacked-via cell design, the internal routing becomes very challenging due to the large density of via connections in each metal layer. By bypassing intermediate metal layers, the use of SuperVias can contribute to routing decongestion and can also help relaxing the secondary design rules (such as metal tip-to-tip) in the metal layers. As such, it has the potential to enable track height reduction towards 4.5 tracks.
SuperVias can potentially also be part of buried power rail constructs – which is another scaling booster for future technology nodes. Power rails provide power to the different components of the chip and are traditionally implemented as metal lines in the chip’s middle-of-line (i.e., the Mint and M1 layers). There, however, they occupy considerable space making pin access difficult. In a buried power rail construct, the power rails are buried in the chip’s front-end-of-line to help free up routing resources for the interconnects. This, in turn, can help minimize the standard cell height. One of the challenges is however to deliver power to the power rail which is now buried deep inside the front-end-of-line. And this is where the high-aspect-ratio SuperVia can come to the rescue.
First proof-of-concept: 40% lower resistance
In scaled standard cells, the actual length of the interconnect wires in each metal layer is becoming shorter, and this changes the relative importance of the metal wire resistance (being proportional to its length) vs. the ‘vertical’ resistance of the via. For smaller standard cell designs, the latter becomes increasingly important.
For the first time, imec revealed the beneficial impact of a SuperVia structure on the resistance and capacitance of the interconnect scheme in scaled standard cells. When comparing the resistance of the SuperVia to the resistance of a regular stacked via (with equivalent via cross-sectional area), the resistance of the SuperVia turns out to be 40% lower. This can be related to the presence of a single interface between via and metal layer (more specifically, the barrier/liner interface) in the SuperVia scenario, as compared to two interfaces in the stacked-via scenario. An improvement of 10% was found for the capacitance value. This demonstrates the positive impact of the SuperVia on the RC delay issue.
Process flow and fabrication challenges
The imec team, in collaboration with its partners, has fabricated the first high-aspect-ratio SuperVias by using a dual-damascene compatible self-aligned integration scheme – consisting of various lithography, etch and metallization steps. ‘Dual-damascene compatible’ means that the flow makes use of the basic structures of the dual-damascene metallization used for fabricating the metal layers. And this lowers the insertion cost into a standard CMOS interconnect process flow.
At this stage of technology development, however, the SuperVias do not yet meet all technology specifications. Challenges remain with respect to, e.g., the non-uniform ‘landing’ and height of the via (impacting the via resistance), and the selectivity towards the hard mask. Enabling a stable integration will therefore require improvements in various steps of the process flow. Also, specialized metrology will be required to enable in-line monitoring of the various aspects of the SuperVia process development. This will be the subject of future research and development. Furthermore, today’s standard design tools do not support such a construct. Nevertheless, it is believed that enabling the SuperVia construct in the longer run will help to maintain the required area scaling for advanced nodes such as 3nm and beyond.
Want to know more?
- ‘How to solve the back-end-of-line RC delay problem?’, imec magazine
- ‘Imec shows breakthrough in extending interconnects beyond the 3nm technology node’, press release
- ‘Imec extends damascene metallization towards the 3nm technology node’, press release
- The results of this work have recently been presented at the 2018 International Conference on Solid State Devices and Materials (SSDM). The paper ‘CMOS area scaling and the need for high aspect ratio vias’, by B. Briggs et al, can be requested via this link.
Zsolt Tokei is program director nano-interconnects at imec. He joined imec in 1999 and since then held various technical positions in the organization. First as a process engineer and researcher in the field of copper low-k interconnects, then he headed the metal section. Later he became principal scientist, program director nano-interconnects and, in 2016, was appointed distinguished member of technical staff interconnect. He earned a M.S. (1994) in physics from the University Kossuth in Debrecen, Hungary. In the framework of a co-directed thesis between the Hungarian University Kossuth and the French University Aix Marseille-III, he obtained his PhD (1997) in physics and materials science. In 1998 he started working at the Max-Planck Institute of Düsseldorf, Germany, as a post-doctorate researcher. Joining imec, he continued working on a range of interconnect issues including scaling, metallization, electrical characterization, module integration, reliability and system aspects.
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